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[78.54.62.214]) by smtp.gmail.com with ESMTPSA id dy21-20020a05640231f500b00556e497cc96sm183153edb.84.2024.01.08.12.31.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jan 2024 12:31:24 -0800 (PST) Date: Mon, 08 Jan 2024 19:53:38 +0000 From: Bernhard Beschow To: BALATON Zoltan CC: qemu-devel@nongnu.org, Eduardo Habkost , Artyom Tarasenko , =?ISO-8859-1?Q?Marc-Andr=E9_Lureau?= , Fabiano Rosas , Jiaxun Yang , =?ISO-8859-1?Q?C=E9dric_Le_Goater?= , =?ISO-8859-1?Q?Fr=E9d=E9ric_Barrat?= , John Snow , qemu-block@nongnu.org, Kevin Wolf , Thomas Huth , Richard Henderson , Nicholas Piggin , Aleksandar Rikalo , Peter Xu , Leonardo Bras , Paolo Bonzini , "Michael S. Tsirkin" , Juan Quintela , =?ISO-8859-1?Q?Philippe_Mathieu-Daud=E9?= , qemu-ppc@nongnu.org, David Hildenbrand , Marcel Apfelbaum , Sergio Lopez , Hanna Reitz , Mark Cave-Ayland , =?ISO-8859-1?Q?Herv=E9_Poussineau?= Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v4_11/11=5D_hw/isa/vt82c686=3A_Implemen?= =?US-ASCII?Q?t_relocation_and_toggling_of_SuperI/O_functions?= In-Reply-To: <43de62e3-67d0-f013-2f4b-21ec1a78dbee@eik.bme.hu> References: <20240106210531.140542-1-shentey@gmail.com> <20240106210531.140542-12-shentey@gmail.com> <43de62e3-67d0-f013-2f4b-21ec1a78dbee@eik.bme.hu> Message-ID: <953F5075-4774-457F-BC9C-DA021DED8C0F@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=shentey@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Am 7=2E Januar 2024 13:59:44 UTC schrieb BALATON Zoltan : >On Sat, 6 Jan 2024, Bernhard Beschow wrote: >> The VIA south bridges are able to relocate and toggle (enable or disabl= e) their >> SuperI/O functions=2E So far this is hardcoded such that all functions = are always >> enabled and are located at fixed addresses=2E >>=20 >> Some PC BIOSes seem to probe for I/O occupancy before activating such a= function >> and issue an error in case of a conflict=2E Since the functions are cur= rently >> enabled on reset, conflicts are always detected=2E Prevent that by impl= ementing >> relocation and toggling of the SuperI/O functions=2E >>=20 >> Note that all SuperI/O functions are now deactivated upon reset (except= for >> VT82C686B's serial ports where Fuloong 2e's rescue-yl seems to expect t= hem to be >> enabled by default)=2E Rely on firmware to configure the functions acco= rdingly=2E >>=20 >> Signed-off-by: Bernhard Beschow >> --- >> hw/isa/vt82c686=2Ec | 66 ++++++++++++++++++++++++++++++++++++++++------= - >> 1 file changed, 56 insertions(+), 10 deletions(-) >>=20 >> diff --git a/hw/isa/vt82c686=2Ec b/hw/isa/vt82c686=2Ec >> index d3e0f6d01f=2E=2E9f62fb5964 100644 >> --- a/hw/isa/vt82c686=2Ec >> +++ b/hw/isa/vt82c686=2Ec >> @@ -15,6 +15,9 @@ >>=20 >> #include "qemu/osdep=2Eh" >> #include "hw/isa/vt82c686=2Eh" >> +#include "hw/block/fdc=2Eh" >> +#include "hw/char/parallel-isa=2Eh" >> +#include "hw/char/serial=2Eh" >> #include "hw/pci/pci=2Eh" >> #include "hw/qdev-properties=2Eh" >> #include "hw/ide/pci=2Eh" >> @@ -323,6 +326,18 @@ static uint64_t via_superio_cfg_read(void *opaque,= hwaddr addr, unsigned size) >> return val; >> } >>=20 >> +static void via_superio_devices_enable(ViaSuperIOState *s, uint8_t dat= a) >> +{ >> + ISASuperIOClass *ic =3D ISA_SUPERIO_GET_CLASS(s); >> + size_t i; > >The expected value for i is 0 or 1 (maybe up to 3 sometimes it there are = more serial ports in a chip)=2E so why use such big type? serial=2Ecount is of type size_t, that's why I chose it=2E Let me know if = you still want an int, otherwise I'd leave it as is=2E Best regards, Bernhard > This should just be int=2E Newly it's also allowed to declare it within = the for so if you want that you could do so but I have no preference on tha= t and declaring it here is also OK=2E Otherwise: > >Reviewed-by: BALATON Zoltan > >> + >> + isa_parallel_set_enabled(s->superio=2Eparallel[0], (data & 0x3) != =3D 3); >> + for (i =3D 0; i < ic->serial=2Ecount; i++) { >> + isa_serial_set_enabled(s->superio=2Eserial[i], data & BIT(i + = 2)); >> + } >> + isa_fdc_set_enabled(s->superio=2Efloppy, data & BIT(4)); >> +} >> + >> static void via_superio_class_init(ObjectClass *klass, void *data) >> { >> DeviceClass *dc =3D DEVICE_CLASS(klass); >> @@ -368,7 +383,25 @@ static void vt82c686b_superio_cfg_write(void *opaq= ue, hwaddr addr, >> case 0xfd =2E=2E=2E 0xff: >> /* ignore write to read only registers */ >> return; >> - /* case 0xe6 =2E=2E=2E 0xe8: Should set base port of parallel and = serial */ >> + case 0xe2: >> + data &=3D 0x1f; >> + via_superio_devices_enable(sc, data); >> + break; >> + case 0xe3: >> + data &=3D 0xfc; >> + isa_fdc_set_iobase(sc->superio=2Efloppy, data << 2); >> + break; >> + case 0xe6: >> + isa_parallel_set_iobase(sc->superio=2Eparallel[0], data << 2); >> + break; >> + case 0xe7: >> + data &=3D 0xfe; >> + isa_serial_set_iobase(sc->superio=2Eserial[0], data << 2); >> + break; >> + case 0xe8: >> + data &=3D 0xfe; >> + isa_serial_set_iobase(sc->superio=2Eserial[1], data << 2); >> + break; >> default: >> qemu_log_mask(LOG_UNIMP, >> "via_superio_cfg: unimplemented register 0x%x\n",= idx); >> @@ -395,9 +428,14 @@ static void vt82c686b_superio_reset(DeviceState *d= ev) >> /* Device ID */ >> vt82c686b_superio_cfg_write(s, 0, 0xe0, 1); >> vt82c686b_superio_cfg_write(s, 1, 0x3c, 1); >> - /* Function select - all disabled */ >> + /* >> + * Function select - only serial enabled >> + * Fuloong 2e's rescue-yl prints to the serial console w/o enablin= g it=2E This >> + * suggests that the serial ports are enabled by default, so overr= ide the >> + * datasheet=2E >> + */ >> vt82c686b_superio_cfg_write(s, 0, 0xe2, 1); >> - vt82c686b_superio_cfg_write(s, 1, 0x03, 1); >> + vt82c686b_superio_cfg_write(s, 1, 0x0f, 1); >> /* Floppy ctrl base addr 0x3f0-7 */ >> vt82c686b_superio_cfg_write(s, 0, 0xe3, 1); >> vt82c686b_superio_cfg_write(s, 1, 0xfc, 1); >> @@ -465,6 +503,21 @@ static void vt8231_superio_cfg_write(void *opaque,= hwaddr addr, >> case 0xfd: >> /* ignore write to read only registers */ >> return; >> + case 0xf2: >> + data &=3D 0x17; >> + via_superio_devices_enable(sc, data); >> + break; >> + case 0xf4: >> + data &=3D 0xfe; >> + isa_serial_set_iobase(sc->superio=2Eserial[0], data << 2); >> + break; >> + case 0xf6: >> + isa_parallel_set_iobase(sc->superio=2Eparallel[0], data << 2); >> + break; >> + case 0xf7: >> + data &=3D 0xfc; >> + isa_fdc_set_iobase(sc->superio=2Efloppy, data << 2); >> + break; >> default: >> qemu_log_mask(LOG_UNIMP, >> "via_superio_cfg: unimplemented register 0x%x\n",= idx); >> @@ -513,12 +566,6 @@ static void vt8231_superio_init(Object *obj) >> VIA_SUPERIO(obj)->io_ops =3D &vt8231_superio_cfg_ops; >> } >>=20 >> -static uint16_t vt8231_superio_serial_iobase(ISASuperIODevice *sio, >> - uint8_t index) >> -{ >> - return 0x2f8; /* FIXME: This should be settable via registers = f2-f4 */ >> -} >> - >> static void vt8231_superio_class_init(ObjectClass *klass, void *data) >> { >> DeviceClass *dc =3D DEVICE_CLASS(klass); >> @@ -526,7 +573,6 @@ static void vt8231_superio_class_init(ObjectClass *= klass, void *data) >>=20 >> dc->reset =3D vt8231_superio_reset; >> sc->serial=2Ecount =3D 1; >> - sc->serial=2Eget_iobase =3D vt8231_superio_serial_iobase; >> sc->parallel=2Ecount =3D 1; >> sc->ide=2Ecount =3D 0; /* emulated by via-ide */ >> sc->floppy=2Ecount =3D 1; >>=20