From: "Cédric Le Goater" <clg@kaod.org>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Christophe Leroy" <christophe.leroy@csgroup.eu>,
"qemu-ppc@nongnu.org" <qemu-ppc@nongnu.org>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: Thomas Huth <thuth@redhat.com>,
Daniel Henrique Barboza <danielhb413@gmail.com>,
Greg Kurz <groug@kaod.org>,
David Gibson <david@gibson.dropbear.id.au>
Subject: Re: [PATCH 00/15] ppc/ppc405: decade cleanup
Date: Mon, 20 Dec 2021 19:18:05 +0100 [thread overview]
Message-ID: <957bd09f-dde5-aa2f-bc7e-dcb7827bdbc0@kaod.org> (raw)
In-Reply-To: <b4d0eb8f-a349-51df-3b4c-6081d55f5a04@amsat.org>
On 12/20/21 19:07, Philippe Mathieu-Daudé wrote:
> On 12/20/21 09:33, Cédric Le Goater wrote:
>>>
>>> Don't know if this is the reason of our problems but I think there is
>>> something to investigate around timer interrupts:
>>>
>>>
>>> / # cat /proc/interrupts
>>> CPU0
>>> 16: 68 UIC 1 Level serial
>>> LOC: 0 Local timer interrupts for timer event device
>>> LOC: 0 Local timer interrupts for others
>>> SPU: 0 Spurious interrupts
>>> PMI: 0 Performance monitoring interrupts
>>> MCE: 0 Machine check exceptions
>>>
>>> Any idea what the problem can be ? How does QEMU generates timer
>>> interrupts ?
>>
>> I did some archeology and fixed the 405 timer (PIT). Please see commits
>> in :
>>
>> https://github.com/legoater/qemu/commits/ppc405
>>
>> but we are still getting segfaults. At some point /init tries to load from
>> fffffe04 which is obviously wrong.
>
> Fetching an u32 value from a missing ROM?
hmm, I don't think so. Here are some logs.
Thanks,
C.
....
mmu40x_get_physical_address: access granted b7bd6000 => 00000000005ba000 13 0
0xb7bd6744: 80dffff8 lwz r6, -8(r31)
0xb7bd6748: 7ce63850 subf r7, r6, r7
0xb7bd674c: 80a70008 lwz r5, 8(r7)
0xb7bd6750: 7c843214 add r4, r4, r6
0xb7bd6754: 8065000c lwz r3, 0xc(r5)
0xb7bd6758: 80c7000c lwz r6, 0xc(r7)
0xb7bd675c: 7c071800 cmpw r7, r3
0xb7bd6760: 41a20008 beq 0xb7bd6768
ppcemb_tlb_check: TLB 14 address fffffe04 PID 3 <=> c0000000 ff000000 0 f
ppcemb_tlb_check: TLB 15 address fffffe04 PID 3 <=> c7000000 ff000000 0 f
ppcemb_tlb_check: TLB 16 address fffffe04 PID 3 <=> c1000000 ff000000 0 f
ppcemb_tlb_check: TLB 17 address fffffe04 PID 3 <=> b7bdc000 fffff000 2 d
ppcemb_tlb_check: TLB 19 address fffffe04 PID 3 <=> b7c30000 fffff000 2 b
ppcemb_tlb_check: TLB 20 address fffffe04 PID 3 <=> bfe4f000 fffff000 2 9
ppcemb_tlb_check: TLB 22 address fffffe04 PID 3 <=> b7c32000 fffff000 2 b
ppcemb_tlb_check: TLB 23 address fffffe04 PID 3 <=> b7bff000 fffff000 2 d
ppcemb_tlb_check: TLB 24 address fffffe04 PID 3 <=> 00913000 fffff000 2 d
ppcemb_tlb_check: TLB 25 address fffffe04 PID 3 <=> b7c64000 fffff000 3 b
ppcemb_tlb_check: TLB 26 address fffffe04 PID 3 <=> b7c2f000 fffff000 3 9
ppcemb_tlb_check: TLB 27 address fffffe04 PID 3 <=> b7bf5000 fffff000 3 d
ppcemb_tlb_check: TLB 28 address fffffe04 PID 3 <=> bfe4f000 fffff000 3 b
ppcemb_tlb_check: TLB 30 address fffffe04 PID 3 <=> 009bc000 fffff000 2 9
ppcemb_tlb_check: TLB 32 address fffffe04 PID 3 <=> 009c1000 fffff000 2 b
ppcemb_tlb_check: TLB 33 address fffffe04 PID 3 <=> 009c0000 fffff000 2 9
ppcemb_tlb_check: TLB 34 address fffffe04 PID 3 <=> 00970000 fffff000 2 d
ppcemb_tlb_check: TLB 35 address fffffe04 PID 3 <=> b7c44000 fffff000 3 b
ppcemb_tlb_check: TLB 36 address fffffe04 PID 3 <=> 00911000 fffff000 3 d
ppcemb_tlb_check: TLB 37 address fffffe04 PID 3 <=> 00912000 fffff000 3 d
ppcemb_tlb_check: TLB 38 address fffffe04 PID 3 <=> 0090e000 fffff000 3 d
ppcemb_tlb_check: TLB 39 address fffffe04 PID 3 <=> 00919000 fffff000 2 d
ppcemb_tlb_check: TLB 40 address fffffe04 PID 3 <=> 00971000 fffff000 2 d
ppcemb_tlb_check: TLB 41 address fffffe04 PID 3 <=> 009bf000 fffff000 2 9
ppcemb_tlb_check: TLB 42 address fffffe04 PID 3 <=> b7ba8000 fffff000 2 d
ppcemb_tlb_check: TLB 43 address fffffe04 PID 3 <=> 009c0000 fffff000 3 b
ppcemb_tlb_check: TLB 44 address fffffe04 PID 3 <=> 0090f000 fffff000 3 d
ppcemb_tlb_check: TLB 45 address fffffe04 PID 3 <=> 00910000 fffff000 3 d
ppcemb_tlb_check: TLB 46 address fffffe04 PID 3 <=> 008d9000 fffff000 3 d
ppcemb_tlb_check: TLB 47 address fffffe04 PID 3 <=> 00976000 fffff000 3 d
ppcemb_tlb_check: TLB 48 address fffffe04 PID 3 <=> b7bf4000 fffff000 3 d
ppcemb_tlb_check: TLB 49 address fffffe04 PID 3 <=> b7bd5000 fffff000 3 d
ppcemb_tlb_check: TLB 50 address fffffe04 PID 3 <=> b7c00000 fffff000 3 d
ppcemb_tlb_check: TLB 51 address fffffe04 PID 3 <=> b7ba7000 fffff000 3 d
ppcemb_tlb_check: TLB 52 address fffffe04 PID 3 <=> 0090d000 fffff000 3 d
ppcemb_tlb_check: TLB 53 address fffffe04 PID 3 <=> 00918000 fffff000 3 d
ppcemb_tlb_check: TLB 54 address fffffe04 PID 3 <=> 0097a000 fffff000 3 d
ppcemb_tlb_check: TLB 55 address fffffe04 PID 3 <=> b7bd6000 fffff000 3 d
ppcemb_tlb_check: TLB 56 address fffffe04 PID 3 <=> b7bf8000 fffff000 3 d
ppcemb_tlb_check: TLB 58 address fffffe04 PID 3 <=> b7c46000 fffff000 3 b
mmu40x_get_physical_address: access refused fffffe04 => ffffffffffffffff 4096 -1
NIP b7bd6744 LR b7bd66cc CTR b7bf471c XER 00000000 CPU#0
MSR 0000c030 HID0 00000300 HF 00004012 iidx 0 didx 0
TB 00000000 984786301 DECR 4294956920
GPR00 00000000b7bd66cc 00000000bfe4f9a0 00000000b7c6b470 0000000000000000
GPR04 00000000000000c8 00000000b7c30124 00000000009c140c 00000000fffffdfc
GPR08 000000002d740000 00000000009c12d0 0000000000000049 00000000bfe4f9a0
GPR12 0000000020004002 00000000009bfa94 0000000000000000 0000000000000000
GPR16 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR24 0000000000000004 00000000bfe4f9f8 00000000009c0054 0000000000000000
GPR28 00000000bfe4f9a8 00000000b7c4642c 00000000b7c2fd58 00000000009c1210
CR 20004002 [ E - - - G - - E ] RES ffffffff
SRR0 b7bd672c SRR1 0000c030 PVR 51210950 VRSAVE 00000000
SPRG0 00000049 SPRG1 bfe4f9a0 SPRG2 bfe4f9a0 SPRG3 00c3ee70
SPRG4 20004002 SPRG5 00000049 SPRG6 00000049 SPRG7 bfe4f9a0
TCR 04000000 TSR c8000000 ESR 00800000 DEAR b7c4642c
EVPR 00000000 SRR2 00000000 SRR3 00000000 PID 00000003
Raise exception at b7bd674c => DTLB (13) error=00
....
prev parent reply other threads:[~2021-12-20 19:41 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-06 10:36 [PATCH 00/15] ppc/ppc405: decade cleanup Cédric Le Goater
2021-12-06 10:36 ` [PATCH 01/15] ppc/ppc405: Change kernel load address Cédric Le Goater
2021-12-06 10:36 ` [PATCH 02/15] ppc: Mark the 'taihu' machine as deprecated Cédric Le Goater
2021-12-23 6:55 ` Philippe Mathieu-Daudé
2021-12-06 10:37 ` [PATCH 03/15] ppc: Add trace-events for DCR accesses Cédric Le Goater
2021-12-06 13:17 ` Philippe Mathieu-Daudé
2021-12-06 10:37 ` [PATCH 04/15] ppc/ppc405: Convert printfs to trace-events Cédric Le Goater
2021-12-06 10:37 ` [PATCH 05/15] ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo() Cédric Le Goater
2021-12-06 13:18 ` Philippe Mathieu-Daudé
2021-12-06 10:37 ` [PATCH 06/15] ppc/ppc405: Change ppc405ep_init() return value Cédric Le Goater
2021-12-06 10:37 ` [PATCH 07/15] ppc/ppc405: Add some address space definitions Cédric Le Goater
2021-12-06 13:20 ` Philippe Mathieu-Daudé
2021-12-06 15:05 ` BALATON Zoltan
2021-12-07 6:46 ` Cédric Le Goater
2021-12-06 10:37 ` [PATCH 08/15] ppc/ppc405: Remove flash support Cédric Le Goater
2021-12-06 10:37 ` [PATCH 09/15] ppc/ppc405: Rework FW load Cédric Le Goater
2021-12-06 10:37 ` [PATCH 10/15] ppc/ppc405: Introduce ppc405_set_default_bootinfo() Cédric Le Goater
2021-12-06 10:37 ` [PATCH 11/15] ppc/ppc405: Fix boot from kernel Cédric Le Goater
2021-12-06 15:16 ` BALATON Zoltan
2021-12-07 6:52 ` Cédric Le Goater
2021-12-06 10:37 ` [PATCH 12/15] ppc/ppc405: Change default PLL values at reset Cédric Le Goater
2021-12-06 10:37 ` [PATCH 13/15] ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information Cédric Le Goater
2021-12-06 13:25 ` Philippe Mathieu-Daudé
2021-12-06 10:37 ` [PATCH 14/15] ppc/ppc405: Add update of bi_procfreq field Cédric Le Goater
2021-12-06 10:37 ` [PATCH 15/15] ppc/ppc405: Update U-Boot board information for hotfoot Cédric Le Goater
2021-12-06 13:27 ` Philippe Mathieu-Daudé
2021-12-06 13:37 ` Cédric Le Goater
2021-12-06 13:40 ` Thomas Huth
2021-12-06 15:20 ` Cédric Le Goater
2021-12-15 16:49 ` [PATCH 00/15] ppc/ppc405: decade cleanup Cédric Le Goater
2021-12-17 16:36 ` Christophe Leroy
2021-12-17 17:18 ` Cédric Le Goater
2021-12-18 9:33 ` Cédric Le Goater
2021-12-20 8:33 ` Cédric Le Goater
2021-12-20 18:07 ` Philippe Mathieu-Daudé
2021-12-20 18:18 ` Cédric Le Goater [this message]
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