From: Mike Kowal <kowal@linux.ibm.com>
To: Nicholas Piggin <npiggin@gmail.com>, qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org, "Frédéric Barrat" <fbarrat@linux.ibm.com>,
"Glenn Miles" <milesg@linux.ibm.com>,
"Caleb Schlossin" <calebs@linux.vnet.ibm.com>
Subject: Re: [PATCH 43/50] ppc/xive: Check TIMA operations validity
Date: Thu, 15 May 2025 10:47:39 -0500 [thread overview]
Message-ID: <958306ea-aef6-4115-a539-4cea9ec3578e@linux.ibm.com> (raw)
In-Reply-To: <20250512031100.439842-44-npiggin@gmail.com>
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
> Certain TIMA operations should only be performed when a ring is valid,
> others when the ring is invalid, and they are considered undefined if
> used incorrectly. Add checks for this condition.
Reviewed-by: Michael Kowal<kowal@linux.ibm.com>
Thanks, MAK
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> hw/intc/xive.c | 196 +++++++++++++++++++++++++-----------------
> include/hw/ppc/xive.h | 1 +
> 2 files changed, 116 insertions(+), 81 deletions(-)
>
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index aeca66e56e..d5bbd8f4c6 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -25,6 +25,19 @@
> /*
> * XIVE Thread Interrupt Management context
> */
> +bool xive_ring_valid(XiveTCTX *tctx, uint8_t ring)
> +{
> + uint8_t cur_ring;
> +
> + for (cur_ring = ring; cur_ring <= TM_QW3_HV_PHYS;
> + cur_ring += XIVE_TM_RING_SIZE) {
> + if (!(tctx->regs[cur_ring + TM_WORD2] & 0x80)) {
> + return false;
> + }
> + }
> + return true;
> +}
> +
> bool xive_nsr_indicates_exception(uint8_t ring, uint8_t nsr)
> {
> switch (ring) {
> @@ -663,6 +676,8 @@ typedef struct XiveTmOp {
> uint8_t page_offset;
> uint32_t op_offset;
> unsigned size;
> + bool hw_ok;
> + bool sw_ok;
> void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx,
> hwaddr offset,
> uint64_t value, unsigned size);
> @@ -675,34 +690,34 @@ static const XiveTmOp xive_tm_operations[] = {
> * MMIOs below 2K : raw values and special operations without side
> * effects
> */
> - { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr,
> - NULL },
> - { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx,
> - NULL },
> - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr,
> - NULL },
> - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push,
> - NULL },
> - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL,
> - xive_tm_vt_poll },
> + { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, true, true,
> + xive_tm_set_os_cppr, NULL },
> + { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, true, true,
> + xive_tm_push_os_ctx, NULL },
> + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, true, true,
> + xive_tm_set_hv_cppr, NULL },
> + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, false, true,
> + xive_tm_vt_push, NULL },
> + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, true, true,
> + NULL, xive_tm_vt_poll },
>
> /* MMIOs above 2K : special operations with side effects */
> - { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL,
> - xive_tm_ack_os_reg },
> - { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending,
> - NULL },
> - { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL,
> - xive_tm_pull_os_ctx },
> - { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL,
> - xive_tm_pull_os_ctx },
> - { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL,
> - xive_tm_ack_hv_reg },
> - { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL,
> - xive_tm_pull_pool_ctx },
> - { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL,
> - xive_tm_pull_pool_ctx },
> - { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL,
> - xive_tm_pull_phys_ctx },
> + { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, true, false,
> + NULL, xive_tm_ack_os_reg },
> + { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, true, false,
> + xive_tm_set_os_pending, NULL },
> + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, true, false,
> + NULL, xive_tm_pull_os_ctx },
> + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, true, false,
> + NULL, xive_tm_pull_os_ctx },
> + { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, true, false,
> + NULL, xive_tm_ack_hv_reg },
> + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, true, false,
> + NULL, xive_tm_pull_pool_ctx },
> + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, true, false,
> + NULL, xive_tm_pull_pool_ctx },
> + { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, true, false,
> + NULL, xive_tm_pull_phys_ctx },
> };
>
> static const XiveTmOp xive2_tm_operations[] = {
> @@ -710,52 +725,48 @@ static const XiveTmOp xive2_tm_operations[] = {
> * MMIOs below 2K : raw values and special operations without side
> * effects
> */
> - { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive2_tm_set_os_cppr,
> - NULL },
> - { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx,
> - NULL },
> - { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 8, xive2_tm_push_os_ctx,
> - NULL },
> - { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, xive_tm_set_os_lgs,
> - NULL },
> - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive2_tm_set_hv_cppr,
> - NULL },
> - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push,
> - NULL },
> - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL,
> - xive_tm_vt_poll },
> - { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_T, 1, xive2_tm_set_hv_target,
> - NULL },
> + { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, true, true,
> + xive2_tm_set_os_cppr, NULL },
> + { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, true, true,
> + xive2_tm_push_os_ctx, NULL },
> + { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 8, true, true,
> + xive2_tm_push_os_ctx, NULL },
> + { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, true, true,
> + xive_tm_set_os_lgs, NULL },
> + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, true, true,
> + xive2_tm_set_hv_cppr, NULL },
> + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, true, true,
> + NULL, xive_tm_vt_poll },
> + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_T, 1, true, true,
> + xive2_tm_set_hv_target, NULL },
>
> /* MMIOs above 2K : special operations with side effects */
> - { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL,
> - xive_tm_ack_os_reg },
> - { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending,
> - NULL },
> - { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_G2, 4, NULL,
> - xive2_tm_pull_os_ctx },
> - { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL,
> - xive2_tm_pull_os_ctx },
> - { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL,
> - xive2_tm_pull_os_ctx },
> - { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL,
> - xive_tm_ack_hv_reg },
> - { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX_G2, 4, NULL,
> - xive2_tm_pull_pool_ctx },
> - { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL,
> - xive2_tm_pull_pool_ctx },
> - { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL,
> - xive2_tm_pull_pool_ctx },
> - { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_OL, 1, xive2_tm_pull_os_ctx_ol,
> - NULL },
> - { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_G2, 4, NULL,
> - xive2_tm_pull_phys_ctx },
> - { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, NULL,
> - xive2_tm_pull_phys_ctx },
> - { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_OL, 1, xive2_tm_pull_phys_ctx_ol,
> - NULL },
> - { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_EL, 1, xive2_tm_ack_os_el,
> - NULL },
> + { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, true, false,
> + NULL, xive_tm_ack_os_reg },
> + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_G2, 4, true, false,
> + NULL, xive2_tm_pull_os_ctx },
> + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, true, false,
> + NULL, xive2_tm_pull_os_ctx },
> + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, true, false,
> + NULL, xive2_tm_pull_os_ctx },
> + { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, true, false,
> + NULL, xive_tm_ack_hv_reg },
> + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX_G2, 4, true, false,
> + NULL, xive2_tm_pull_pool_ctx },
> + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, true, false,
> + NULL, xive2_tm_pull_pool_ctx },
> + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, true, false,
> + NULL, xive2_tm_pull_pool_ctx },
> + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX_OL, 1, true, false,
> + xive2_tm_pull_os_ctx_ol, NULL },
> + { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_G2, 4, true, false,
> + NULL, xive2_tm_pull_phys_ctx },
> + { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX, 1, true, false,
> + NULL, xive2_tm_pull_phys_ctx },
> + { XIVE_TM_HV_PAGE, TM_SPC_PULL_PHYS_CTX_OL, 1, true, false,
> + xive2_tm_pull_phys_ctx_ol, NULL },
> + { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_EL, 1, true, false,
> + xive2_tm_ack_os_el, NULL },
> };
>
> static const XiveTmOp *xive_tm_find_op(XivePresenter *xptr, hwaddr offset,
> @@ -797,18 +808,28 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
> uint64_t value, unsigned size)
> {
> const XiveTmOp *xto;
> + uint8_t ring = offset & TM_RING_OFFSET;
> + bool is_valid = xive_ring_valid(tctx, ring);
> + bool hw_owned = is_valid;
>
> trace_xive_tctx_tm_write(tctx->cs->cpu_index, offset, size, value);
>
> - /*
> - * TODO: check V bit in Q[0-3]W2
> - */
> -
> /*
> * First, check for special operations in the 2K region
> */
> + xto = xive_tm_find_op(tctx->xptr, offset, size, true);
> + if (xto) {
> + if (hw_owned && !xto->hw_ok) {
> + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: undefined write to HW TIMA "
> + "@%"HWADDR_PRIx" size %d\n", offset, size);
> + }
> + if (!hw_owned && !xto->sw_ok) {
> + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: undefined write to SW TIMA "
> + "@%"HWADDR_PRIx" size %d\n", offset, size);
> + }
> + }
> +
> if (offset & TM_SPECIAL_OP) {
> - xto = xive_tm_find_op(tctx->xptr, offset, size, true);
> if (!xto) {
> qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA "
> "@%"HWADDR_PRIx" size %d\n", offset, size);
> @@ -821,7 +842,6 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
> /*
> * Then, for special operations in the region below 2K.
> */
> - xto = xive_tm_find_op(tctx->xptr, offset, size, true);
> if (xto) {
> xto->write_handler(xptr, tctx, offset, value, size);
> return;
> @@ -830,6 +850,11 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
> /*
> * Finish with raw access to the register values
> */
> + if (hw_owned) {
> + /* Store context operations are dangerous when context is valid */
> + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: undefined write to HW TIMA "
> + "@%"HWADDR_PRIx" size %d\n", offset, size);
> + }
> xive_tm_raw_write(tctx, offset, value, size);
> }
>
> @@ -837,17 +862,27 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
> unsigned size)
> {
> const XiveTmOp *xto;
> + uint8_t ring = offset & TM_RING_OFFSET;
> + bool is_valid = xive_ring_valid(tctx, ring);
> + bool hw_owned = is_valid;
> uint64_t ret;
>
> - /*
> - * TODO: check V bit in Q[0-3]W2
> - */
> + xto = xive_tm_find_op(tctx->xptr, offset, size, false);
> + if (xto) {
> + if (hw_owned && !xto->hw_ok) {
> + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: undefined read to HW TIMA "
> + "@%"HWADDR_PRIx" size %d\n", offset, size);
> + }
> + if (!hw_owned && !xto->sw_ok) {
> + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: undefined read to SW TIMA "
> + "@%"HWADDR_PRIx" size %d\n", offset, size);
> + }
> + }
>
> /*
> * First, check for special operations in the 2K region
> */
> if (offset & TM_SPECIAL_OP) {
> - xto = xive_tm_find_op(tctx->xptr, offset, size, false);
> if (!xto) {
> qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to TIMA"
> "@%"HWADDR_PRIx" size %d\n", offset, size);
> @@ -860,7 +895,6 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
> /*
> * Then, for special operations in the region below 2K.
> */
> - xto = xive_tm_find_op(tctx->xptr, offset, size, false);
> if (xto) {
> ret = xto->read_handler(xptr, tctx, offset, size);
> goto out;
> diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
> index 2372d1014b..b7ca8544e4 100644
> --- a/include/hw/ppc/xive.h
> +++ b/include/hw/ppc/xive.h
> @@ -365,6 +365,7 @@ static inline uint32_t xive_tctx_word2(uint8_t *ring)
> return *((uint32_t *) &ring[TM_WORD2]);
> }
>
> +bool xive_ring_valid(XiveTCTX *tctx, uint8_t ring);
> bool xive_nsr_indicates_exception(uint8_t ring, uint8_t nsr);
> bool xive_nsr_indicates_group_exception(uint8_t ring, uint8_t nsr);
> uint8_t xive_nsr_exception_ring(uint8_t ring, uint8_t nsr);
next prev parent reply other threads:[~2025-05-15 15:49 UTC|newest]
Thread overview: 192+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-12 3:10 [PATCH 00/50] ppc/xive: updates for PowerVM Nicholas Piggin
2025-05-12 3:10 ` [PATCH 01/50] ppc/xive: Fix xive trace event output Nicholas Piggin
2025-05-14 14:26 ` Caleb Schlossin
2025-05-14 18:41 ` Mike Kowal
2025-05-15 15:30 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 02/50] ppc/xive: Report access size in XIVE TM operation error logs Nicholas Piggin
2025-05-14 14:27 ` Caleb Schlossin
2025-05-14 18:42 ` Mike Kowal
2025-05-15 15:31 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 03/50] ppc/xive2: Fix calculation of END queue sizes Nicholas Piggin
2025-05-14 14:27 ` Caleb Schlossin
2025-05-14 18:45 ` Mike Kowal
2025-05-16 0:06 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 04/50] ppc/xive2: Remote VSDs need to match on forwarding address Nicholas Piggin
2025-05-14 14:27 ` Caleb Schlossin
2025-05-14 18:46 ` Mike Kowal
2025-05-15 15:34 ` Miles Glenn
2025-05-16 0:08 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 05/50] ppc/xive2: fix context push calculation of IPB priority Nicholas Piggin
2025-05-14 14:30 ` Caleb Schlossin
2025-05-14 18:48 ` Mike Kowal
2025-05-15 15:36 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 06/50] ppc/xive: Fix PHYS NSR ring matching Nicholas Piggin
2025-05-14 14:30 ` Caleb Schlossin
2025-05-14 18:49 ` Mike Kowal
2025-05-15 15:39 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 07/50] ppc/xive2: Reset Generation Flipped bit on END Cache Watch Nicholas Piggin
2025-05-14 14:30 ` Caleb Schlossin
2025-05-14 18:50 ` Mike Kowal
2025-05-15 15:41 ` Miles Glenn
2025-05-16 0:09 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 08/50] ppc/xive2: Use fair irq target search algorithm Nicholas Piggin
2025-05-14 14:31 ` Caleb Schlossin
2025-05-14 18:51 ` Mike Kowal
2025-05-15 15:42 ` Miles Glenn
2025-05-16 0:12 ` Nicholas Piggin
2025-05-16 16:22 ` Mike Kowal
2025-05-12 3:10 ` [PATCH 09/50] ppc/xive2: Fix irq preempted by lower priority group irq Nicholas Piggin
2025-05-14 14:31 ` Caleb Schlossin
2025-05-14 18:52 ` Mike Kowal
2025-05-16 0:12 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 10/50] ppc/xive2: Fix treatment of PIPR in CPPR update Nicholas Piggin
2025-05-14 14:32 ` Caleb Schlossin
2025-05-14 18:53 ` Mike Kowal
2025-05-16 0:15 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 11/50] ppc/xive2: Do not present group interrupt on OS-push if precluded by CPPR Nicholas Piggin
2025-05-14 14:32 ` Caleb Schlossin
2025-05-14 18:54 ` Mike Kowal
2025-05-15 15:43 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 12/50] ppc/xive2: Set CPPR delivery should account for group priority Nicholas Piggin
2025-05-14 14:33 ` Caleb Schlossin
2025-05-14 18:57 ` Mike Kowal
2025-05-15 15:45 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 13/50] ppc/xive: tctx_notify should clear the precluded interrupt Nicholas Piggin
2025-05-14 14:33 ` Caleb Schlossin
2025-05-14 18:58 ` Mike Kowal
2025-05-15 15:46 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 14/50] ppc/xive: Explicitly zero NSR after accepting Nicholas Piggin
2025-05-14 14:34 ` Caleb Schlossin
2025-05-14 19:07 ` Mike Kowal
2025-05-15 23:31 ` Nicholas Piggin
2025-05-15 15:47 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 15/50] ppc/xive: Move NSR decoding into helper functions Nicholas Piggin
2025-05-14 14:35 ` Caleb Schlossin
2025-05-14 19:04 ` Mike Kowal
2025-05-15 15:48 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 16/50] ppc/xive: Fix pulling pool and phys contexts Nicholas Piggin
2025-05-14 14:36 ` Caleb Schlossin
2025-05-14 19:01 ` Mike Kowal
2025-05-15 15:49 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 17/50] pnv/xive2: Support ESB Escalation Nicholas Piggin
2025-05-14 14:36 ` Caleb Schlossin
2025-05-14 19:00 ` Mike Kowal
2025-05-16 0:05 ` Nicholas Piggin
2025-05-16 15:44 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 18/50] pnv/xive2: Print value in invalid register write logging Nicholas Piggin
2025-05-14 14:36 ` Caleb Schlossin
2025-05-14 19:09 ` Mike Kowal
2025-05-15 15:50 ` Miles Glenn
2025-05-16 0:15 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 19/50] pnv/xive2: VC_ENDC_WATCH_SPEC regs should read back WATCH_FULL Nicholas Piggin
2025-05-14 14:37 ` Caleb Schlossin
2025-05-14 19:10 ` Mike Kowal
2025-05-15 15:51 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 20/50] pnv/xive2: Permit valid writes to VC/PC Flush Control registers Nicholas Piggin
2025-05-14 14:37 ` Caleb Schlossin
2025-05-14 19:11 ` Mike Kowal
2025-05-15 15:52 ` Miles Glenn
2025-05-16 0:18 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 21/50] ppc/xive2: add interrupt priority configuration flags Nicholas Piggin
2025-05-14 19:41 ` Mike Kowal
2025-05-16 0:18 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 22/50] ppc/xive2: Support redistribution of group interrupts Nicholas Piggin
2025-05-14 19:42 ` Mike Kowal
2025-05-16 0:19 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 23/50] ppc/xive: Add more interrupt notification tracing Nicholas Piggin
2025-05-14 19:46 ` Mike Kowal
2025-05-16 0:19 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 24/50] ppc/xive2: Improve pool regs variable name Nicholas Piggin
2025-05-14 19:47 ` Mike Kowal
2025-05-16 0:19 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 25/50] ppc/xive2: Implement "Ack OS IRQ to even report line" TIMA op Nicholas Piggin
2025-05-14 19:48 ` Mike Kowal
2025-05-16 0:20 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 26/50] ppc/xive2: Redistribute group interrupt precluded by CPPR update Nicholas Piggin
2025-05-14 19:48 ` Mike Kowal
2025-05-16 0:20 ` Nicholas Piggin
2025-05-12 3:10 ` [PATCH 27/50] ppc/xive2: redistribute irqs for pool and phys ctx pull Nicholas Piggin
2025-05-14 19:51 ` Mike Kowal
2025-05-12 3:10 ` [PATCH 28/50] ppc/xive: Change presenter .match_nvt to match not present Nicholas Piggin
2025-05-14 19:54 ` Mike Kowal
2025-05-15 23:40 ` Nicholas Piggin
2025-05-15 15:53 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 29/50] ppc/xive2: Redistribute group interrupt preempted by higher priority interrupt Nicholas Piggin
2025-05-14 19:55 ` Mike Kowal
2025-05-15 15:54 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 30/50] ppc/xive: Add xive_tctx_pipr_present() to present new interrupt Nicholas Piggin
2025-05-14 20:10 ` Mike Kowal
2025-05-15 15:21 ` Mike Kowal
2025-05-15 23:51 ` Nicholas Piggin
2025-05-15 23:43 ` Nicholas Piggin
2025-05-15 15:55 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 31/50] ppc/xive: Fix high prio group interrupt being preempted by low prio VP Nicholas Piggin
2025-05-15 15:21 ` Mike Kowal
2025-05-15 15:55 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 32/50] ppc/xive: Split xive recompute from IPB function Nicholas Piggin
2025-05-14 20:42 ` Mike Kowal
2025-05-15 23:46 ` Nicholas Piggin
2025-05-15 15:56 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 33/50] ppc/xive: tctx signaling registers rework Nicholas Piggin
2025-05-14 20:49 ` Mike Kowal
2025-05-15 15:58 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 34/50] ppc/xive: tctx_accept only lower irq line if an interrupt was presented Nicholas Piggin
2025-05-15 15:16 ` Mike Kowal
2025-05-15 23:50 ` Nicholas Piggin
2025-05-15 16:04 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 35/50] ppc/xive: Add xive_tctx_pipr_set() helper function Nicholas Piggin
2025-05-15 15:18 ` Mike Kowal
2025-05-15 16:05 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 36/50] ppc/xive2: split tctx presentation processing from set CPPR Nicholas Piggin
2025-05-15 15:24 ` Mike Kowal
2025-05-15 16:06 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 37/50] ppc/xive2: Consolidate presentation processing in context push Nicholas Piggin
2025-05-15 15:25 ` Mike Kowal
2025-05-15 16:06 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 38/50] ppc/xive2: Avoid needless interrupt re-check on CPPR set Nicholas Piggin
2025-05-15 15:26 ` Mike Kowal
2025-05-15 16:07 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 39/50] ppc/xive: Assert group interrupts were redistributed Nicholas Piggin
2025-05-15 15:28 ` Mike Kowal
2025-05-15 16:08 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 40/50] ppc/xive2: implement NVP context save restore for POOL ring Nicholas Piggin
2025-05-15 15:36 ` Mike Kowal
2025-05-15 16:09 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 41/50] ppc/xive2: Prevent pulling of pool context losing phys interrupt Nicholas Piggin
2025-05-15 15:43 ` Mike Kowal
2025-05-15 16:10 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 42/50] ppc/xive: Redistribute phys after pulling of pool context Nicholas Piggin
2025-05-15 15:46 ` Mike Kowal
2025-05-15 16:11 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 43/50] ppc/xive: Check TIMA operations validity Nicholas Piggin
2025-05-15 15:47 ` Mike Kowal [this message]
2025-05-15 16:12 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 44/50] ppc/xive2: Implement pool context push TIMA op Nicholas Piggin
2025-05-15 15:48 ` Mike Kowal
2025-05-15 16:13 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 45/50] ppc/xive2: redistribute group interrupts on context push Nicholas Piggin
2025-05-15 15:44 ` Mike Kowal
2025-05-15 16:13 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 46/50] ppc/xive2: Implement set_os_pending TIMA op Nicholas Piggin
2025-05-15 15:49 ` Mike Kowal
2025-05-15 16:14 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 47/50] ppc/xive2: Implement POOL LGS push " Nicholas Piggin
2025-05-15 15:50 ` Mike Kowal
2025-05-15 16:15 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 48/50] ppc/xive2: Implement PHYS ring VP " Nicholas Piggin
2025-05-15 15:50 ` Mike Kowal
2025-05-15 16:16 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 49/50] ppc/xive: Split need_resend into restore_nvp Nicholas Piggin
2025-05-15 15:57 ` Mike Kowal
2025-05-15 16:16 ` Miles Glenn
2025-05-12 3:10 ` [PATCH 50/50] ppc/xive2: Enable lower level contexts on VP push Nicholas Piggin
2025-05-15 15:54 ` Mike Kowal
2025-05-15 16:17 ` Miles Glenn
2025-05-15 15:36 ` [PATCH 00/50] ppc/xive: updates for PowerVM Cédric Le Goater
2025-05-16 1:29 ` Nicholas Piggin
2025-07-20 21:26 ` Cédric Le Goater
2025-08-04 17:37 ` Miles Glenn
2025-08-05 5:09 ` Cédric Le Goater
2025-08-05 15:52 ` Miles Glenn
2025-08-05 20:09 ` Cédric Le Goater
2025-07-03 9:37 ` Gautam Menghani
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