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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477b102a3a1sm7970765e9.9.2025.11.18.12.17.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Nov 2025 12:17:30 -0800 (PST) Message-ID: <958b25bf-c930-4117-8378-e9f87621d2c3@linaro.org> Date: Tue, 18 Nov 2025 21:17:29 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 01/13] target/riscv: Really use little endianness for 128-bit loads/stores Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: Christoph Muellner , Heinrich Schuchardt , Palmer Dabbelt , Alistair Francis , Liu Zhiwei , Anton Johansson , Valentin Haudiquet , Weiwei Li , qemu-riscv@nongnu.org, Daniel Henrique Barboza , =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= References: <20251010155045.78220-1-philmd@linaro.org> <20251010155045.78220-2-philmd@linaro.org> <88f8d901-b7b4-47e6-b209-f9375c5b95e1@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <88f8d901-b7b4-47e6-b209-f9375c5b95e1@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Richard, [Dropping Fabien Portas from Cc due to bouncing email] On 10/10/25 20:44, Richard Henderson wrote: > On 10/10/25 08:50, Philippe Mathieu-Daudé wrote: >> Per commit a2f827ff4f4 ("target/riscv: accessors to registers upper >> part and 128-bit load/store") description: >> >>   > The 128-bit ISA adds ldu, lq and sq. We provide support for these >>   > instructions. Note that (a) we compute only 64-bit addresses to >>   > actually access memory, cowardly utilizing the existing address >>   > translation mechanism of QEMU, and (b) we assume for now >>   > little-endian memory accesses. >> >>     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ >> >> However this commit used MO_TE (target endianness) for the >> gen_load_i128() and gen_store_i128() helpers. Likely it was >> unnoticed because current targets are only built using little >> endianness: >> >>    $ git grep -L TARGET_BIG_ENDIAN=y configs/targets/riscv* >>    configs/targets/riscv32-linux-user.mak >>    configs/targets/riscv32-softmmu.mak >>    configs/targets/riscv64-bsd-user.mak >>    configs/targets/riscv64-linux-user.mak >>    configs/targets/riscv64-softmmu.mak >> >> Replace by MO_TE -> MO_LE to really use little endianness. >> >> Cc: Fabien Portas >> Cc: Frédéric Pétrot >> Fixes: a2f827ff4f4 ("target/riscv: accessors to registers upper part >> and 128-bit load/store") >> Signed-off-by: Philippe Mathieu-Daudé >> --- >>   target/riscv/insn_trans/trans_rvi.c.inc | 12 ++++++++---- >>   1 file changed, 8 insertions(+), 4 deletions(-) >> >> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/ >> insn_trans/trans_rvi.c.inc >> index b9c71604687..df0b555176a 100644 >> --- a/target/riscv/insn_trans/trans_rvi.c.inc >> +++ b/target/riscv/insn_trans/trans_rvi.c.inc >> @@ -389,9 +389,11 @@ static bool gen_load_i128(DisasContext *ctx, >> arg_lb *a, MemOp memop) >>           } >>       } else { >>           /* assume little-endian memory access for now */ >> -        tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, MO_TEUQ); >> +        MemOp memop = MO_LEUQ; >> + >> +        tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, memop); >>           tcg_gen_addi_tl(addrl, addrl, 8); >> -        tcg_gen_qemu_ld_tl(desth, addrl, ctx->mem_idx, MO_TEUQ); >> +        tcg_gen_qemu_ld_tl(desth, addrl, ctx->mem_idx, memop); >>       } >>       gen_set_gpr128(ctx, a->rd, destl, desth); >> @@ -494,9 +496,11 @@ static bool gen_store_i128(DisasContext *ctx, >> arg_sb *a, MemOp memop) >>           tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop); >>       } else { >>           /* little-endian memory access assumed for now */ >> -        tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, MO_TEUQ); >> +        MemOp memop = MO_LEUQ; >> + >> +        tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop); >>           tcg_gen_addi_tl(addrl, addrl, 8); >> -        tcg_gen_qemu_st_tl(src2h, addrl, ctx->mem_idx, MO_TEUQ); >> +        tcg_gen_qemu_st_tl(src2h, addrl, ctx->mem_idx, memop); >>       } >>       return true; >>   } > > We fix this to use tcg_gen_qemu_{ld,st}_i128. IIUC the target doesn't use TCGv_i128 but a pair of TCGv_i64 named cpu_gpr[] and cpu_gprh[] (i.e. see how gen_set_gpr128() set them). Using tcg_gen_qemu_{ld,st}_i128() makes sense but implies a huge internals rewrite, which 1/ I'm not willing to do without tests and 2/ I won't have time to do because of priorities. Could we proceed with this simple patch meanwhile? Regards, Phil.