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Mon, 6 Oct 2025 15:46:51 +0000 (GMT) Content-Type: multipart/alternative; boundary="------------H52FfIKnaaqLxZoR2GANZQOE" Message-ID: <95b3bfd6-e1a4-4b19-a86b-cc666da6eb30@linux.ibm.com> Date: Mon, 6 Oct 2025 10:46:51 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 4/8] ppc/pnv: Add XIVE2 controller to Power11 To: Aditya Gupta , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Nicholas Piggin , Harsh Prateek Bora Cc: Mahesh J Salgaonkar , Madhavan Srinivasan , Gautam Menghani , Miles Glenn , Ganesh Goudar , qemu-devel@nongnu.org, qemu-ppc@nongnu.org References: <20250925173049.891406-1-adityag@linux.ibm.com> <20250925173049.891406-5-adityag@linux.ibm.com> Content-Language: en-US From: Mike Kowal In-Reply-To: <20250925173049.891406-5-adityag@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: L625E1ngWhXgx0kW744MkE1LkZ_ePXfZ X-Authority-Analysis: v=2.4 cv=BpiQAIX5 c=1 sm=1 tr=0 ts=68e3e470 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=x6icFKpwvdMA:10 a=r77TgQKjGQsHNAKrUKIA:9 a=VnNF1IyMAAAA:8 a=20KFwNOVAAAA:8 a=p8j9cQVM6DJJbO-JqHcA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=H1shgiIZPKTCiYXe3LcA:9 a=OdyiT02D3D_q1XT8:21 a=_W_S_7VecoQA:10 a=lqcHg5cX4UMA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA0MDAyMiBTYWx0ZWRfXzCWNhnFnaRz4 97MLFo7FZZb9uIW3cgRxtv1+ZshbUY76qMtSH/yGfoouP2ovLcowsijRmrD1Hor6knCzhS3K6os 8U1BsH5dfKsYtJWYVyIixg62vnIUIep4ND4ouZ2y1coFKuYDpihOPHkqf0AjJQa/xXo5lctu4oM nZA4KQsBPFPmWrD0dCme4Y66WjMXLVXcs/NOy1cgxj5dgtxaq6pHYrOoHa16kNlRdU3qrptmxYi sBEVPVC46lpahtBhcwrKeKsAmhyG2Q+okHL9my/bqOYkLcU+yUZTUVNZo9GEAIn63r73gMAmr2r x7B+ApkmFKC+hXNCZbt6bi2/23LJ+ckUPfSApcVkF4AibX+VWHmCA9r+z3aoUAPvPFD2wkZj3+O YOqmIp9Xt92hgf6dRmfTAJ+8QWFwoQ== X-Proofpoint-ORIG-GUID: w5ISR7_We3EnKMmZi-M7Vh6ZEniu8-Gm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-06_05,2025-10-02_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2510040022 Received-SPF: pass client-ip=148.163.158.5; envelope-from=kowal@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This is a multi-part message in MIME format. --------------H52FfIKnaaqLxZoR2GANZQOE Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 9/25/2025 12:30 PM, Aditya Gupta wrote: > Add a XIVE2 controller to Power11 chip and machine. > The controller has the same logic as Power10. Reviewed-by: Michael Kowal > > Reviewed-by: Cédric Le Goater > Signed-off-by: Aditya Gupta > --- > hw/ppc/pnv.c | 121 ++++++++++++++++++++++++++++++++++++++++++- > include/hw/ppc/pnv.h | 18 +++++++ > 2 files changed, 138 insertions(+), 1 deletion(-) > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index a4fdf59207fa..8097d3c09a2f 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -976,6 +976,7 @@ static void pnv_chip_power11_pic_print_info(PnvChip *chip, GString *buf) > { > Pnv11Chip *chip11 = PNV11_CHIP(chip); > > + pnv_xive2_pic_print_info(&chip11->xive, buf); > pnv_psi_pic_print_info(&chip11->psi, buf); > } > > @@ -1491,6 +1492,50 @@ static void *pnv_chip_power10_intc_get(PnvChip *chip) > return &PNV10_CHIP(chip)->xive; > } > > +static void pnv_chip_power11_intc_create(PnvChip *chip, PowerPCCPU *cpu, > + Error **errp) > +{ > + Pnv11Chip *chip11 = PNV11_CHIP(chip); > + Error *local_err = NULL; > + Object *obj; > + PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); > + > + /* > + * The core creates its interrupt presenter but the XIVE2 interrupt > + * controller object is initialized afterwards. Hopefully, it's > + * only used at runtime. > + */ > + obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip11->xive), > + &local_err); > + if (local_err) { > + error_propagate(errp, local_err); > + return; > + } > + > + pnv_cpu->intc = obj; > +} > + > +static void pnv_chip_power11_intc_reset(PnvChip *chip, PowerPCCPU *cpu) > +{ > + PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); > + > + xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); > +} > + > +static void pnv_chip_power11_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) > +{ > + PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); > + > + xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); > + pnv_cpu->intc = NULL; > +} > + > +static void pnv_chip_power11_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, > + GString *buf) > +{ > + xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); > +} > + > static void *pnv_chip_power11_intc_get(PnvChip *chip) > { > return &PNV11_CHIP(chip)->xive; > @@ -2443,6 +2488,10 @@ static void pnv_chip_power11_instance_init(Object *obj) > object_initialize_child(obj, "occ", &chip11->occ, TYPE_PNV10_OCC); > object_initialize_child(obj, "sbe", &chip11->sbe, TYPE_PNV10_SBE); > object_initialize_child(obj, "homer", &chip11->homer, TYPE_PNV10_HOMER); > + > + object_initialize_child(obj, "xive", &chip11->xive, TYPE_PNV_XIVE2); > + object_property_add_alias(obj, "xive-fabric", OBJECT(&chip11->xive), > + "xive-fabric"); > object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet, > TYPE_PNV_N1_CHIPLET); > > @@ -2518,7 +2567,26 @@ static void pnv_chip_power11_realize(DeviceState *dev, Error **errp) > return; > } > > - /* WIP: XIVE added in future patch */ > + /* XIVE2 interrupt controller */ > + object_property_set_int(OBJECT(&chip11->xive), "ic-bar", > + PNV11_XIVE2_IC_BASE(chip), &error_fatal); > + object_property_set_int(OBJECT(&chip11->xive), "esb-bar", > + PNV11_XIVE2_ESB_BASE(chip), &error_fatal); > + object_property_set_int(OBJECT(&chip11->xive), "end-bar", > + PNV11_XIVE2_END_BASE(chip), &error_fatal); > + object_property_set_int(OBJECT(&chip11->xive), "nvpg-bar", > + PNV11_XIVE2_NVPG_BASE(chip), &error_fatal); > + object_property_set_int(OBJECT(&chip11->xive), "nvc-bar", > + PNV11_XIVE2_NVC_BASE(chip), &error_fatal); > + object_property_set_int(OBJECT(&chip11->xive), "tm-bar", > + PNV11_XIVE2_TM_BASE(chip), &error_fatal); > + object_property_set_link(OBJECT(&chip11->xive), "chip", OBJECT(chip), > + &error_abort); > + if (!sysbus_realize(SYS_BUS_DEVICE(&chip11->xive), errp)) { > + return; > + } > + pnv_xscom_add_subregion(chip, PNV11_XSCOM_XIVE2_BASE, > + &chip11->xive.xscom_regs); > > /* Processor Service Interface (PSI) Host Bridge */ > object_property_set_int(OBJECT(&chip11->psi), "bar", > @@ -2720,6 +2788,10 @@ static void pnv_chip_power11_class_init(ObjectClass *klass, const void *data) > k->chip_cfam_id = 0x220da04980000000ull; /* P11 DD2.0 (with NX) */ > k->cores_mask = POWER11_CORE_MASK; > k->get_pir_tir = pnv_get_pir_tir_p10; > + k->intc_create = pnv_chip_power11_intc_create; > + k->intc_reset = pnv_chip_power11_intc_reset; > + k->intc_destroy = pnv_chip_power11_intc_destroy; > + k->intc_print_info = pnv_chip_power11_intc_print_info; > k->intc_get = pnv_chip_power11_intc_get; > k->isa_create = pnv_chip_power11_isa_create; > k->dt_populate = pnv_chip_power11_dt_populate; > @@ -3073,6 +3145,45 @@ static int pnv10_xive_broadcast(XiveFabric *xfb, > return 0; > } > > +static bool pnv11_xive_match_nvt(XiveFabric *xfb, uint8_t format, > + uint8_t nvt_blk, uint32_t nvt_idx, > + bool crowd, bool cam_ignore, uint8_t priority, > + uint32_t logic_serv, > + XiveTCTXMatch *match) > +{ > + PnvMachineState *pnv = PNV_MACHINE(xfb); > + int i; > + > + for (i = 0; i < pnv->num_chips; i++) { > + Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]); > + XivePresenter *xptr = XIVE_PRESENTER(&chip11->xive); > + XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); > + > + xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, > + cam_ignore, priority, logic_serv, match); > + } > + > + return !!match->count; > +} > + > +static int pnv11_xive_broadcast(XiveFabric *xfb, > + uint8_t nvt_blk, uint32_t nvt_idx, > + bool crowd, bool cam_ignore, > + uint8_t priority) > +{ > + PnvMachineState *pnv = PNV_MACHINE(xfb); > + int i; > + > + for (i = 0; i < pnv->num_chips; i++) { > + Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]); > + XivePresenter *xptr = XIVE_PRESENTER(&chip11->xive); > + XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); > + > + xpc->broadcast(xptr, nvt_blk, nvt_idx, crowd, cam_ignore, priority); > + } > + return 0; > +} > + > static bool pnv_machine_get_big_core(Object *obj, Error **errp) > { > PnvMachineState *pnv = PNV_MACHINE(obj); > @@ -3251,6 +3362,7 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, const void *data) > { > MachineClass *mc = MACHINE_CLASS(oc); > PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); > + XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); > static const char compat[] = "qemu,powernv11\0ibm,powernv"; > > pmc->compat = compat; > @@ -3260,6 +3372,9 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, const void *data) > pmc->quirk_tb_big_core = true; > pmc->dt_power_mgt = pnv_dt_power_mgt; > > + xfc->match_nvt = pnv11_xive_match_nvt; > + xfc->broadcast = pnv11_xive_broadcast; > + > mc->desc = "IBM PowerNV (Non-Virtualized) Power11"; > mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11_v2.0"); > > @@ -3393,6 +3508,10 @@ static const TypeInfo types[] = { > .name = MACHINE_TYPE_NAME("powernv11"), > .parent = TYPE_PNV_MACHINE, > .class_init = pnv_machine_power11_class_init, > + .interfaces = (InterfaceInfo[]) { > + { TYPE_XIVE_FABRIC }, > + { }, > + }, > }, > { > .name = MACHINE_TYPE_NAME("powernv10-rainier"), > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index f0002627bcab..cbdddfc73cd4 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -270,6 +270,24 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); > #define PNV11_PSIHB_SIZE PNV10_PSIHB_SIZE > #define PNV11_PSIHB_BASE(chip) PNV10_PSIHB_BASE(chip) > > +#define PNV11_XIVE2_IC_SIZE PNV10_XIVE2_IC_SIZE > +#define PNV11_XIVE2_IC_BASE(chip) PNV10_XIVE2_IC_BASE(chip) > + > +#define PNV11_XIVE2_TM_SIZE PNV10_XIVE2_TM_SIZE > +#define PNV11_XIVE2_TM_BASE(chip) PNV10_XIVE2_TM_BASE(chip) > + > +#define PNV11_XIVE2_NVC_SIZE PNV10_XIVE2_NVC_SIZE > +#define PNV11_XIVE2_NVC_BASE(chip) PNV10_XIVE2_NVC_BASE(chip) > + > +#define PNV11_XIVE2_NVPG_SIZE PNV10_XIVE2_NVPG_SIZE > +#define PNV11_XIVE2_NVPG_BASE(chip) PNV10_XIVE2_NVPG_BASE(chip) > + > +#define PNV11_XIVE2_ESB_SIZE PNV10_XIVE2_ESB_SIZE > +#define PNV11_XIVE2_ESB_BASE(chip) PNV10_XIVE2_ESB_BASE(chip) > + > +#define PNV11_XIVE2_END_SIZE PNV10_XIVE2_END_SIZE > +#define PNV11_XIVE2_END_BASE(chip) PNV10_XIVE2_END_BASE(chip) > + > #define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip) > > #endif /* PPC_PNV_H */ --------------H52FfIKnaaqLxZoR2GANZQOE Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit


On 9/25/2025 12:30 PM, Aditya Gupta wrote:
Add a XIVE2 controller to Power11 chip and machine.
The controller has the same logic as Power10.

Reviewed-by: Michael Kowal <kowal@linux.ibm.com>

Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
 hw/ppc/pnv.c         | 121 ++++++++++++++++++++++++++++++++++++++++++-
 include/hw/ppc/pnv.h |  18 +++++++
 2 files changed, 138 insertions(+), 1 deletion(-)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index a4fdf59207fa..8097d3c09a2f 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -976,6 +976,7 @@ static void pnv_chip_power11_pic_print_info(PnvChip *chip, GString *buf)
 {
     Pnv11Chip *chip11 = PNV11_CHIP(chip);
 
+    pnv_xive2_pic_print_info(&chip11->xive, buf);
     pnv_psi_pic_print_info(&chip11->psi, buf);
 }
 
@@ -1491,6 +1492,50 @@ static void *pnv_chip_power10_intc_get(PnvChip *chip)
     return &PNV10_CHIP(chip)->xive;
 }
 
+static void pnv_chip_power11_intc_create(PnvChip *chip, PowerPCCPU *cpu,
+                                        Error **errp)
+{
+    Pnv11Chip *chip11 = PNV11_CHIP(chip);
+    Error *local_err = NULL;
+    Object *obj;
+    PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
+
+    /*
+     * The core creates its interrupt presenter but the XIVE2 interrupt
+     * controller object is initialized afterwards. Hopefully, it's
+     * only used at runtime.
+     */
+    obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip11->xive),
+                           &local_err);
+    if (local_err) {
+        error_propagate(errp, local_err);
+        return;
+    }
+
+    pnv_cpu->intc = obj;
+}
+
+static void pnv_chip_power11_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
+{
+    PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
+
+    xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
+}
+
+static void pnv_chip_power11_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
+{
+    PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
+
+    xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
+    pnv_cpu->intc = NULL;
+}
+
+static void pnv_chip_power11_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
+                                             GString *buf)
+{
+    xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
+}
+
 static void *pnv_chip_power11_intc_get(PnvChip *chip)
 {
     return &PNV11_CHIP(chip)->xive;
@@ -2443,6 +2488,10 @@ static void pnv_chip_power11_instance_init(Object *obj)
     object_initialize_child(obj, "occ",  &chip11->occ, TYPE_PNV10_OCC);
     object_initialize_child(obj, "sbe",  &chip11->sbe, TYPE_PNV10_SBE);
     object_initialize_child(obj, "homer", &chip11->homer, TYPE_PNV10_HOMER);
+
+    object_initialize_child(obj, "xive", &chip11->xive, TYPE_PNV_XIVE2);
+    object_property_add_alias(obj, "xive-fabric", OBJECT(&chip11->xive),
+                              "xive-fabric");
     object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet,
                             TYPE_PNV_N1_CHIPLET);
 
@@ -2518,7 +2567,26 @@ static void pnv_chip_power11_realize(DeviceState *dev, Error **errp)
         return;
     }
 
-    /* WIP: XIVE added in future patch */
+    /* XIVE2 interrupt controller */
+    object_property_set_int(OBJECT(&chip11->xive), "ic-bar",
+                            PNV11_XIVE2_IC_BASE(chip), &error_fatal);
+    object_property_set_int(OBJECT(&chip11->xive), "esb-bar",
+                            PNV11_XIVE2_ESB_BASE(chip), &error_fatal);
+    object_property_set_int(OBJECT(&chip11->xive), "end-bar",
+                            PNV11_XIVE2_END_BASE(chip), &error_fatal);
+    object_property_set_int(OBJECT(&chip11->xive), "nvpg-bar",
+                            PNV11_XIVE2_NVPG_BASE(chip), &error_fatal);
+    object_property_set_int(OBJECT(&chip11->xive), "nvc-bar",
+                            PNV11_XIVE2_NVC_BASE(chip), &error_fatal);
+    object_property_set_int(OBJECT(&chip11->xive), "tm-bar",
+                            PNV11_XIVE2_TM_BASE(chip), &error_fatal);
+    object_property_set_link(OBJECT(&chip11->xive), "chip", OBJECT(chip),
+                             &error_abort);
+    if (!sysbus_realize(SYS_BUS_DEVICE(&chip11->xive), errp)) {
+        return;
+    }
+    pnv_xscom_add_subregion(chip, PNV11_XSCOM_XIVE2_BASE,
+                            &chip11->xive.xscom_regs);
 
     /* Processor Service Interface (PSI) Host Bridge */
     object_property_set_int(OBJECT(&chip11->psi), "bar",
@@ -2720,6 +2788,10 @@ static void pnv_chip_power11_class_init(ObjectClass *klass, const void *data)
     k->chip_cfam_id = 0x220da04980000000ull; /* P11 DD2.0 (with NX) */
     k->cores_mask = POWER11_CORE_MASK;
     k->get_pir_tir = pnv_get_pir_tir_p10;
+    k->intc_create = pnv_chip_power11_intc_create;
+    k->intc_reset = pnv_chip_power11_intc_reset;
+    k->intc_destroy = pnv_chip_power11_intc_destroy;
+    k->intc_print_info = pnv_chip_power11_intc_print_info;
     k->intc_get = pnv_chip_power11_intc_get;
     k->isa_create = pnv_chip_power11_isa_create;
     k->dt_populate = pnv_chip_power11_dt_populate;
@@ -3073,6 +3145,45 @@ static int pnv10_xive_broadcast(XiveFabric *xfb,
     return 0;
 }
 
+static bool pnv11_xive_match_nvt(XiveFabric *xfb, uint8_t format,
+                                 uint8_t nvt_blk, uint32_t nvt_idx,
+                                 bool crowd, bool cam_ignore, uint8_t priority,
+                                 uint32_t logic_serv,
+                                 XiveTCTXMatch *match)
+{
+    PnvMachineState *pnv = PNV_MACHINE(xfb);
+    int i;
+
+    for (i = 0; i < pnv->num_chips; i++) {
+        Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]);
+        XivePresenter *xptr = XIVE_PRESENTER(&chip11->xive);
+        XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
+
+        xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd,
+                       cam_ignore, priority, logic_serv, match);
+    }
+
+    return !!match->count;
+}
+
+static int pnv11_xive_broadcast(XiveFabric *xfb,
+                                uint8_t nvt_blk, uint32_t nvt_idx,
+                                bool crowd, bool cam_ignore,
+                                uint8_t priority)
+{
+    PnvMachineState *pnv = PNV_MACHINE(xfb);
+    int i;
+
+    for (i = 0; i < pnv->num_chips; i++) {
+        Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]);
+        XivePresenter *xptr = XIVE_PRESENTER(&chip11->xive);
+        XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
+
+        xpc->broadcast(xptr, nvt_blk, nvt_idx, crowd, cam_ignore, priority);
+    }
+    return 0;
+}
+
 static bool pnv_machine_get_big_core(Object *obj, Error **errp)
 {
     PnvMachineState *pnv = PNV_MACHINE(obj);
@@ -3251,6 +3362,7 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, const void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
     PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
+    XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
     static const char compat[] = "qemu,powernv11\0ibm,powernv";
 
     pmc->compat = compat;
@@ -3260,6 +3372,9 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, const void *data)
     pmc->quirk_tb_big_core = true;
     pmc->dt_power_mgt = pnv_dt_power_mgt;
 
+    xfc->match_nvt = pnv11_xive_match_nvt;
+    xfc->broadcast = pnv11_xive_broadcast;
+
     mc->desc = "IBM PowerNV (Non-Virtualized) Power11";
     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11_v2.0");
 
@@ -3393,6 +3508,10 @@ static const TypeInfo types[] = {
         .name          = MACHINE_TYPE_NAME("powernv11"),
         .parent        = TYPE_PNV_MACHINE,
         .class_init    = pnv_machine_power11_class_init,
+        .interfaces = (InterfaceInfo[]) {
+            { TYPE_XIVE_FABRIC },
+            { },
+        },
     },
     {
         .name          = MACHINE_TYPE_NAME("powernv10-rainier"),
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index f0002627bcab..cbdddfc73cd4 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -270,6 +270,24 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
 #define PNV11_PSIHB_SIZE            PNV10_PSIHB_SIZE
 #define PNV11_PSIHB_BASE(chip)      PNV10_PSIHB_BASE(chip)
 
+#define PNV11_XIVE2_IC_SIZE         PNV10_XIVE2_IC_SIZE
+#define PNV11_XIVE2_IC_BASE(chip)   PNV10_XIVE2_IC_BASE(chip)
+
+#define PNV11_XIVE2_TM_SIZE         PNV10_XIVE2_TM_SIZE
+#define PNV11_XIVE2_TM_BASE(chip)   PNV10_XIVE2_TM_BASE(chip)
+
+#define PNV11_XIVE2_NVC_SIZE        PNV10_XIVE2_NVC_SIZE
+#define PNV11_XIVE2_NVC_BASE(chip)  PNV10_XIVE2_NVC_BASE(chip)
+
+#define PNV11_XIVE2_NVPG_SIZE       PNV10_XIVE2_NVPG_SIZE
+#define PNV11_XIVE2_NVPG_BASE(chip) PNV10_XIVE2_NVPG_BASE(chip)
+
+#define PNV11_XIVE2_ESB_SIZE        PNV10_XIVE2_ESB_SIZE
+#define PNV11_XIVE2_ESB_BASE(chip)  PNV10_XIVE2_ESB_BASE(chip)
+
+#define PNV11_XIVE2_END_SIZE        PNV10_XIVE2_END_SIZE
+#define PNV11_XIVE2_END_BASE(chip)  PNV10_XIVE2_END_BASE(chip)
+
 #define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip)
 
 #endif /* PPC_PNV_H */
--------------H52FfIKnaaqLxZoR2GANZQOE--