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[176.184.13.61]) by smtp.gmail.com with ESMTPSA id h9-20020a05600c314900b0040b32edf626sm11521547wmo.31.2023.11.28.03.24.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Nov 2023 03:24:05 -0800 (PST) Message-ID: <95cc7c22-939f-4ce0-aecd-d0ff7b0e7c9c@linaro.org> Date: Tue, 28 Nov 2023 12:24:02 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/4] target/arm: Add support for DC CVAP & DC CVADP ins Content-Language: en-US To: peter.maydell@linaro.org, richard.henderson@linaro.org, Beata Michalska , qemu-devel@nongnu.org, =?UTF-8?Q?Alex_Benn=C3=A9e?= Cc: quintela@redhat.com, dgilbert@redhat.com, shameerali.kolothum.thodi@huawei.com, eric.auger@redhat.com, qemu-arm@nongnu.org, pbonzini@redhat.com References: <20191105234100.22052-1-beata.michalska@linaro.org> <20191105234100.22052-5-beata.michalska@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20191105234100.22052-5-beata.michalska@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=philmd@linaro.org; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, On 6/11/19 00:41, Beata Michalska wrote: > ARMv8.2 introduced support for Data Cache Clean instructions > to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence) > - DV CVADP. Both specify conceptual points in a memory system where all writes > that are to reach them are considered persistent. > The support provided considers both to be actually the same so there is no > distinction between the two. If none is available (there is no backing store > for given memory) both will result in Data Cache Clean up to the point of > coherency. Otherwise sync for the specified range shall be performed. > > Signed-off-by: Beata Michalska > --- > linux-user/elfload.c | 2 ++ > target/arm/cpu.h | 10 ++++++++++ > target/arm/cpu64.c | 1 + > target/arm/helper.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 69 insertions(+) > +#ifndef CONFIG_USER_ONLY > +static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, > + uint64_t value) > +{ > + ARMCPU *cpu = env_archcpu(env); > + /* CTR_EL0 System register -> DminLine, bits [19:16] */ > + uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); > + uint64_t vaddr_in = (uint64_t) value; > + uint64_t vaddr = vaddr_in & ~(dline_size - 1); > + void *haddr; > + int mem_idx = cpu_mmu_index(env, false); > + > + /* This won't be crossing page boundaries */ > + haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC()); > + if (haddr) { > + > + ram_addr_t offset; > + MemoryRegion *mr; > + > + /* RCU lock is already being held */ > + mr = memory_region_from_host(haddr, &offset); > + > + if (mr) { > + memory_region_do_writeback(mr, offset, dline_size); > + } > + } > +} > +#ifndef CONFIG_USER_ONLY > + /* Data Cache clean instructions up to PoP */ > + if (cpu_isar_feature(aa64_dcpop, cpu)) { Am I correct understanding this is a TCG-only feature? > + define_one_arm_cp_reg(cpu, dcpop_reg); > + > + if (cpu_isar_feature(aa64_dcpodp, cpu)) { > + define_one_arm_cp_reg(cpu, dcpodp_reg); > + } > + } > +#endif /*CONFIG_USER_ONLY*/ > #endif > > /*