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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390e47a6739sm1294657f8f.22.2025.02.27.00.42.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Feb 2025 00:42:34 -0800 (PST) Message-ID: <96003060-0292-4e5b-b8cb-9d6b956e25c0@linaro.org> Date: Thu, 27 Feb 2025 09:42:33 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 002/162] tcg: Remove INDEX_op_ext{8,16,32}* To: Richard Henderson , qemu-devel@nongnu.org References: <20250216231012.2808572-1-richard.henderson@linaro.org> <20250216231012.2808572-3-richard.henderson@linaro.org> <7035dcac-380b-49c6-a091-29afcdb631c2@linaro.org> <471ba4e3-be12-4571-9165-80b780a6e9a1@linaro.org> <7af17a02-84f0-4f5e-91bf-f1bd19d1e5ab@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <7af17a02-84f0-4f5e-91bf-f1bd19d1e5ab@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 26/2/25 22:52, Richard Henderson wrote: > On 2/26/25 13:51, Philippe Mathieu-Daudé wrote: >> On 22/2/25 18:41, Richard Henderson wrote: >>> On 2/20/25 14:17, Philippe Mathieu-Daudé wrote: >>>>> @@ -1794,23 +1715,19 @@ void tcg_gen_andi_i64(TCGv_i64 ret, >>>>> TCGv_i64 arg1, int64_t arg2) >>>>>       case -1: >>>>>           tcg_gen_mov_i64(ret, arg1); >>>>>           return; >>>>> -    case 0xff: >>>>> -        /* Don't recurse with tcg_gen_ext8u_i64.  */ >>>>> -        if (TCG_TARGET_HAS_ext8u_i64) { >>>>> -            tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg1); >>>>> -            return; >>>>> -        } >>>>> -        break; >>>>> -    case 0xffff: >>>>> -        if (TCG_TARGET_HAS_ext16u_i64) { >>>>> -            tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg1); >>>>> -            return; >>>>> -        } >>>>> -        break; >>>>> -    case 0xffffffffu: >>>>> -        if (TCG_TARGET_HAS_ext32u_i64) { >>>>> -            tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg1); >>>>> -            return; >>>>> +    default: >>>>> +        /* >>>>> +         * Canonicalize on extract, if valid.  This aids x86 with its >>>>> +         * 2 operand MOVZBL and 2 operand AND, selecting the >>>>> TCGOpcode >>>>> +         * which does not require matching operands.  Other >>>>> backends can >>>>> +         * trivially expand the extract to AND during code >>>>> generation. >>>>> +         */ >>>> >>>> Could also use s/0/ofs/ like for 32-bit. >>> >>> Pardon?  Are you confusing the tcg_gen_andi_{i32,i64} changes >>> with the tcg_gen_{s}extract_{i32,i64} changes? >>> >>> This andi_i64 hunk exactly matches the andi_i32 hunk. >> >> I am thinking of handling ofs > 0: >> >>             unsigned ofs = ctz64(arg2); >>             int64_t val = arg2 >> ofs; >> >>             if (!(val & (val + 1))) { >>                 unsigned len = cto64(val); >>                 if (TCG_TARGET_extract_valid(TCG_TYPE_I64, ofs, len)) { >>                     tcg_gen_extract_i64(ret, arg1, ofs, len); >>                     return; >>                 } >>             } >> > > This is AND.  There is no shift involved.  If ofs != 0, you cannot use > extract. 🤦 right...