From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E48B1CA1005 for ; Tue, 2 Sep 2025 07:37:14 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1utLZ4-0002o8-VC; Tue, 02 Sep 2025 03:36:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1utLYz-0002nX-EY; Tue, 02 Sep 2025 03:36:23 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1utLYw-000807-S5; Tue, 02 Sep 2025 03:36:21 -0400 Received: from mail.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4cGHbw4dsSz4w9x; Tue, 2 Sep 2025 17:36:12 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mail.ozlabs.org (Postfix) with ESMTPSA id 4cGHbs02vwz4w9t; Tue, 2 Sep 2025 17:36:08 +1000 (AEST) Message-ID: <96254526-949b-4db2-971e-fd0ea9f71e98@kaod.org> Date: Tue, 2 Sep 2025 09:36:05 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [SPAM] [PATCH v1 04/21] hw/arm/aspeed_ast27x0-ssp: Switch SSP memory to SDRAM and use dram_container for remap support To: Jamin Lin , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" Cc: troy_lee@aspeedtech.com References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> <20250717034054.1903991-5-jamin_lin@aspeedtech.com> From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Content-Language: en-US, fr Autocrypt: addr=clg@kaod.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=Sj0j=3N=kaod.org=clg@ozlabs.org; helo=mail.ozlabs.org X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/17/25 05:40, Jamin Lin wrote: > According to the AST2700 design, the SSP coprocessor uses its own SDRAM > instead of SRAM. Additionally, all three coprocessors—SSP, TSP, and PSP—share > a common SRAM block. In the previous implementation, the SSP memory region > was labeled and sized as "SRAM", but in practice it was being used as SSP's > local SDRAM. So the SSP coprocessor has no SRAM ? > > This commit updates the SSP memory mapping to reflect the correct hardware > design: > > - Replace the SRAM region with a "512MB SDRAM" region starting at 0x0. Is 512MB a real HW value ? Thanks, C. > - Rename the internal variable from "sram" to "dram_container" for clarity. > - Use "AST2700_SSP_SDRAM_SIZE" (512MB) instead of the previous 32MB SRAM size. > - Map the new region using "ASPEED_DEV_SDRAM" instead of "ASPEED_DEV_SRAM". > > This change also prepares for future enhancements where PSP DRAM will be > remapped into this SSP SDRAM container using subregions at specific offsets. > Using "dram_container" makes it easier to manage aliases and remap logic. > > Signed-off-by: Jamin Lin > --- > hw/arm/aspeed_ast27x0-ssp.c | 20 ++++++++++---------- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c > index 80ec5996c1..9641e27de1 100644 > --- a/hw/arm/aspeed_ast27x0-ssp.c > +++ b/hw/arm/aspeed_ast27x0-ssp.c > @@ -15,10 +15,10 @@ > #include "hw/misc/unimp.h" > #include "hw/arm/aspeed_soc.h" > > -#define AST2700_SSP_RAM_SIZE (32 * MiB) > +#define AST2700_SSP_SDRAM_SIZE (512 * MiB) > > static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = { > - [ASPEED_DEV_SRAM] = 0x00000000, > + [ASPEED_DEV_SDRAM] = 0x00000000, > [ASPEED_DEV_INTC] = 0x72100000, > [ASPEED_DEV_SCU] = 0x72C02000, > [ASPEED_DEV_SCUIO] = 0x74C02000, > @@ -163,7 +163,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp) > AspeedSoCState *s = ASPEED_SOC(dev_soc); > AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); > DeviceState *armv7m; > - g_autofree char *sram_name = NULL; > + g_autofree char *name = NULL; > int i; > > if (!clock_has_source(s->sysclk)) { > @@ -180,16 +180,17 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp) > OBJECT(s->memory), &error_abort); > sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort); > > - sram_name = g_strdup_printf("aspeed.dram.%d", > - CPU(a->armv7m.cpu)->cpu_index); > + /* SDRAM */ > + name = g_strdup_printf("aspeed.sdram-container.%d", > + CPU(a->armv7m.cpu)->cpu_index); > > - if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, > - errp)) { > + if (!memory_region_init_ram(&s->dram_container, OBJECT(s), name, > + AST2700_SSP_SDRAM_SIZE, errp)) { > return; > } > memory_region_add_subregion(s->memory, > - sc->memmap[ASPEED_DEV_SRAM], > - &s->sram); > + sc->memmap[ASPEED_DEV_SDRAM], > + &s->dram_container); > > /* SCU */ > if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { > @@ -268,7 +269,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass, const void *dat > > sc->valid_cpu_types = valid_cpu_types; > sc->silicon_rev = AST2700_A1_SILICON_REV; > - sc->sram_size = AST2700_SSP_RAM_SIZE; > sc->spis_num = 0; > sc->ehcis_num = 0; > sc->wdts_num = 0;