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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20beef8ea48sm13719805ad.149.2024.10.03.16.08.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Oct 2024 16:08:50 -0700 (PDT) Message-ID: <9635d3ed-b60f-4406-aa57-3d8764b4f5bb@linaro.org> Date: Thu, 3 Oct 2024 16:08:48 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: {PATCH] accel/tcg: Fix CPU specific unaligned behaviour To: Peter Maydell , =?UTF-8?Q?Alex_Benn=C3=A9e?= Cc: Helge Deller , qemu-devel@nongnu.org, linux-parisc@vger.kernel.org References: <87cykimsb9.fsf@draig.linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/2/24 08:47, Peter Maydell wrote: > There's also something curious going on here -- this patch > says "we check alignment before permissions, and that's wrong > on PARISC". But there's a comment in target/arm/ptw.c that > says "we check permissions before alignment, and that's > wrong on Arm": > > * Enable alignment checks on Device memory. > * > * Per R_XCHFJ, this check is mis-ordered. The correct ordering > * for alignment, permission, and stage 2 faults should be: > * - Alignment fault caused by the memory type > * - Permission fault > * - A stage 2 fault on the memory access > * but due to the way the TCG softmmu TLB operates, we will have > * implicitly done the permission check and the stage2 lookup in > * finding the TLB entry, so the alignment check cannot be done sooner. > > So do we check alignment first, or permissions first, or does > the order vary depending on what we're doing? There are two different alignment fault checks. The one for 'alignment fault caused by memory type' is later, after we verify that the TLB entry is for the correct page, which implicitly tests r/w permissions. r~