From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH 10/10] target/arm: Convert Neon one-register-and-immediate insns to decodetree
Date: Fri, 15 May 2020 19:50:57 -0700 [thread overview]
Message-ID: <96522b6c-8d33-51b4-cbdb-e8973f6487b5@linaro.org> (raw)
In-Reply-To: <20200515142056.21346-11-peter.maydell@linaro.org>
On 5/15/20 7:20 AM, Peter Maydell wrote:
> diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
> index f27fe769f85..f4eeb84541f 100644
> --- a/target/arm/translate-neon.inc.c
> +++ b/target/arm/translate-neon.inc.c
> @@ -1821,3 +1821,154 @@ DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos)
> DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos)
> DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero)
> DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero)
> +
> +static uint32_t asimd_imm_const(uint32_t imm, int cmode, int op)
It would be better to match AdvSIMDExpandImm and return uint64_t.
> + case 14:
> + imm |= (imm << 8) | (imm << 16) | (imm << 24);
> + if (op) {
> + imm = ~imm;
> + }
You could then handle case 14 op == 1 properly here,
> +static bool trans_VMVN_14_1r(DisasContext *s, arg_1reg_imm *a)
and you wouldn't have to special case this at all.
> +{
> + # Logic operations, ie not VMOV or VMVN: (cmode & 1) && cmode < 12
> + VORR_1r 1111 001 . 1 . 000 ... .... 0001 0 . 0 1 .... \
> + @1reg_imm cmode=1 op=0
> + VORR_1r 1111 001 . 1 . 000 ... .... 0011 0 . 0 1 .... \
> + @1reg_imm cmode=3 op=0
> + VORR_1r 1111 001 . 1 . 000 ... .... 0101 0 . 0 1 .... \
> + @1reg_imm cmode=5 op=0
> + VORR_1r 1111 001 . 1 . 000 ... .... 0111 0 . 0 1 .... \
> + @1reg_imm cmode=7 op=0
> + VORR_1r 1111 001 . 1 . 000 ... .... 1001 0 . 0 1 .... \
> + @1reg_imm cmode=9 op=0
> + VORR_1r 1111 001 . 1 . 000 ... .... 1011 0 . 0 1 .... \
> + @1reg_imm cmode=11 op=0
> +
> + VBIC_1r 1111 001 . 1 . 000 ... .... 0001 0 . 1 1 .... \
> + @1reg_imm cmode=1 op=1
> + VBIC_1r 1111 001 . 1 . 000 ... .... 0011 0 . 1 1 .... \
> + @1reg_imm cmode=3 op=1
> + VBIC_1r 1111 001 . 1 . 000 ... .... 0101 0 . 1 1 .... \
> + @1reg_imm cmode=5 op=1
> + VBIC_1r 1111 001 . 1 . 000 ... .... 0111 0 . 1 1 .... \
> + @1reg_imm cmode=7 op=1
> + VBIC_1r 1111 001 . 1 . 000 ... .... 1001 0 . 1 1 .... \
> + @1reg_imm cmode=9 op=1
> + VBIC_1r 1111 001 . 1 . 000 ... .... 1011 0 . 1 1 .... \
> + @1reg_imm cmode=11 op=1
> +
> + # A VMVN special case: cmode == 14 op == 1
> + VMVN_14_1r 1111 001 . 1 . 000 ... .... 1110 0 . 1 1 .... \
> + @1reg_imm cmode=14 op=1
> +
> + # VMOV, VMVN: all other cmode/op combinations
> + VMOV_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... \
> + @1reg_imm
> +}
I wonder if it's worth repeating VORR/VBIC so many times.
You can just as well do the (cmode & 1) && cmode < 12 check in the trans_ function.
r~
next prev parent reply other threads:[~2020-05-16 2:51 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-15 14:20 [PATCH 00/10] target/arm: Convert 2-reg-shift and 1-reg-imm Neon insns to decodetree Peter Maydell
2020-05-15 14:20 ` [PATCH 01/10] target/arm: Remove unused GEN_NEON_INTEGER_OP macro Peter Maydell
2020-05-15 22:07 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 02/10] target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree Peter Maydell
2020-05-15 22:16 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 03/10] target/arm: Convert Neon VSHR 2-reg-shift insns " Peter Maydell
2020-05-15 22:33 ` Richard Henderson
2020-05-15 22:48 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 04/10] target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA " Peter Maydell
2020-05-15 22:50 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 05/10] target/arm: Convert VQSHLU, VQSHL " Peter Maydell
2020-05-15 22:55 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 06/10] target/arm: Convert Neon narrowing shifts with op==8 " Peter Maydell
2020-05-16 2:01 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 07/10] target/arm: Convert Neon narrowing shifts with op==9 " Peter Maydell
2020-05-16 2:05 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 08/10] target/arm: Convert Neon VSHLL, VMOVL " Peter Maydell
2020-05-16 2:18 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 09/10] target/arm: Convert VCVT fixed-point ops " Peter Maydell
2020-05-16 2:27 ` Richard Henderson
2020-05-15 14:20 ` [PATCH 10/10] target/arm: Convert Neon one-register-and-immediate insns " Peter Maydell
2020-05-16 2:50 ` Richard Henderson [this message]
2020-05-22 14:31 ` Peter Maydell
2020-05-15 21:32 ` [PATCH 00/10] target/arm: Convert 2-reg-shift and 1-reg-imm Neon " no-reply
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=96522b6c-8d33-51b4-cbdb-e8973f6487b5@linaro.org \
--to=richard.henderson@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).