* [PATCH v4 1/3] target/ppc: Add HASHKEYR and HASHPKEYR SPRs
2022-07-15 20:54 [PATCH v4 0/3] Implement Power ISA 3.1B hash insns Víctor Colombo
@ 2022-07-15 20:54 ` Víctor Colombo
2022-07-18 18:08 ` Lucas Mateus Martins Araujo e Castro
2022-07-15 20:54 ` [PATCH v4 2/3] target/ppc: Implement hashst and hashchk Víctor Colombo
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Víctor Colombo @ 2022-07-15 20:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, victor.colombo,
cohuck, farosas
Add the Special Purpose Registers HASHKEYR and HASHPKEYR, which were
introduced by the Power ISA 3.1B. They are used by the new instructions
hashchk(p) and hashst(p).
The ISA states that the Operating System should generate the value for
these registers when creating a process, so it's its responsability to
do so. We initialize it with 0 for qemu-softmmu, and set a random 64
bits value for linux-user.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
Is the way I did the random number generation ok?
---
target/ppc/cpu.h | 2 ++
target/ppc/cpu_init.c | 28 ++++++++++++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index a4c893cfad..4551d81b5f 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1676,6 +1676,8 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_BOOKE_GIVOR14 (0x1BD)
#define SPR_TIR (0x1BE)
#define SPR_PTCR (0x1D0)
+#define SPR_HASHKEYR (0x1D4)
+#define SPR_HASHPKEYR (0x1D5)
#define SPR_BOOKE_SPEFSCR (0x200)
#define SPR_Exxx_BBEAR (0x201)
#define SPR_Exxx_BBTAR (0x202)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index d1493a660c..29c7752483 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5700,6 +5700,33 @@ static void register_power9_mmu_sprs(CPUPPCState *env)
#endif
}
+static void register_power10_hash_sprs(CPUPPCState *env)
+{
+ /*
+ * it's the OS responsability to generate a random value for the registers
+ * in each process' context. So, initialize it with 0 here.
+ */
+ uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0;
+#if defined(CONFIG_USER_ONLY)
+ /* in linux-user, setup the hash register with a random value */
+ GRand *rand = g_rand_new();
+ hashkeyr_initial_value =
+ ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
+ hashpkeyr_initial_value =
+ ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
+ g_rand_free(rand);
+#endif
+ spr_register(env, SPR_HASHKEYR, "HASHKEYR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ hashkeyr_initial_value);
+ spr_register_hv(env, SPR_HASHPKEYR, "HASHPKEYR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ hashpkeyr_initial_value);
+}
+
/*
* Initialize PMU counter overflow timers for Power8 and
* newer Power chips when using TCG.
@@ -6484,6 +6511,7 @@ static void init_proc_POWER10(CPUPPCState *env)
register_power8_book4_sprs(env);
register_power8_rpr_sprs(env);
register_power9_mmu_sprs(env);
+ register_power10_hash_sprs(env);
/* FIXME: Filter fields properly based on privilege level */
spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v4 1/3] target/ppc: Add HASHKEYR and HASHPKEYR SPRs
2022-07-15 20:54 ` [PATCH v4 1/3] target/ppc: Add HASHKEYR and HASHPKEYR SPRs Víctor Colombo
@ 2022-07-18 18:08 ` Lucas Mateus Martins Araujo e Castro
0 siblings, 0 replies; 8+ messages in thread
From: Lucas Mateus Martins Araujo e Castro @ 2022-07-18 18:08 UTC (permalink / raw)
To: Víctor Colombo, qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, cohuck,
farosas
[-- Attachment #1: Type: text/plain, Size: 3658 bytes --]
On 15/07/2022 17:54, Víctor Colombo wrote:
> Add the Special Purpose Registers HASHKEYR and HASHPKEYR, which were
> introduced by the Power ISA 3.1B. They are used by the new instructions
> hashchk(p) and hashst(p).
>
> The ISA states that the Operating System should generate the value for
> these registers when creating a process, so it's its responsability to
> do so. We initialize it with 0 for qemu-softmmu, and set a random 64
> bits value for linux-user.
>
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
> ---
Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br>
>
> Is the way I did the random number generation ok?
>
> ---
> target/ppc/cpu.h | 2 ++
> target/ppc/cpu_init.c | 28 ++++++++++++++++++++++++++++
> 2 files changed, 30 insertions(+)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index a4c893cfad..4551d81b5f 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1676,6 +1676,8 @@ void ppc_compat_add_property(Object *obj, const char *name,
> #define SPR_BOOKE_GIVOR14 (0x1BD)
> #define SPR_TIR (0x1BE)
> #define SPR_PTCR (0x1D0)
> +#define SPR_HASHKEYR (0x1D4)
> +#define SPR_HASHPKEYR (0x1D5)
> #define SPR_BOOKE_SPEFSCR (0x200)
> #define SPR_Exxx_BBEAR (0x201)
> #define SPR_Exxx_BBTAR (0x202)
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index d1493a660c..29c7752483 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -5700,6 +5700,33 @@ static void register_power9_mmu_sprs(CPUPPCState *env)
> #endif
> }
>
> +static void register_power10_hash_sprs(CPUPPCState *env)
> +{
> + /*
> + * it's the OS responsability to generate a random value for the registers
> + * in each process' context. So, initialize it with 0 here.
> + */
> + uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0;
> +#if defined(CONFIG_USER_ONLY)
> + /* in linux-user, setup the hash register with a random value */
> + GRand *rand = g_rand_new();
> + hashkeyr_initial_value =
> + ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
> + hashpkeyr_initial_value =
> + ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
> + g_rand_free(rand);
> +#endif
> + spr_register(env, SPR_HASHKEYR, "HASHKEYR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + hashkeyr_initial_value);
> + spr_register_hv(env, SPR_HASHPKEYR, "HASHPKEYR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + hashpkeyr_initial_value);
> +}
> +
> /*
> * Initialize PMU counter overflow timers for Power8 and
> * newer Power chips when using TCG.
> @@ -6484,6 +6511,7 @@ static void init_proc_POWER10(CPUPPCState *env)
> register_power8_book4_sprs(env);
> register_power8_rpr_sprs(env);
> register_power9_mmu_sprs(env);
> + register_power10_hash_sprs(env);
>
> /* FIXME: Filter fields properly based on privilege level */
> spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
> --
> 2.25.1
>
>
--
Lucas Mateus M. Araujo e Castro
Instituto de Pesquisas ELDORADO
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
[-- Attachment #2: Type: text/html, Size: 4331 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v4 2/3] target/ppc: Implement hashst and hashchk
2022-07-15 20:54 [PATCH v4 0/3] Implement Power ISA 3.1B hash insns Víctor Colombo
2022-07-15 20:54 ` [PATCH v4 1/3] target/ppc: Add HASHKEYR and HASHPKEYR SPRs Víctor Colombo
@ 2022-07-15 20:54 ` Víctor Colombo
2022-07-18 18:23 ` Lucas Mateus Martins Araujo e Castro
2022-07-15 20:54 ` [PATCH v4 3/3] target/ppc: Implement hashstp and hashchkp Víctor Colombo
2022-09-06 18:44 ` [PATCH v4 0/3] Implement Power ISA 3.1B hash insns Daniel Henrique Barboza
3 siblings, 1 reply; 8+ messages in thread
From: Víctor Colombo @ 2022-07-15 20:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, victor.colombo,
cohuck, farosas
Implementation for instructions hashst and hashchk, which were added
in Power ISA 3.1B.
It was decided to implement the hash algorithm from ground up in this
patch exactly as described in Power ISA.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/excp_helper.c | 82 ++++++++++++++++++++++
target/ppc/helper.h | 2 +
target/ppc/insn32.decode | 8 +++
target/ppc/translate.c | 5 ++
target/ppc/translate/fixedpoint-impl.c.inc | 32 +++++++++
5 files changed, 129 insertions(+)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index cb752b184a..fa5a737e22 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -2174,6 +2174,88 @@ void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
#endif
#endif
+static uint32_t helper_SIMON_LIKE_32_64(uint32_t x, uint64_t key, uint32_t lane)
+{
+ const uint16_t c = 0xfffc;
+ const uint64_t z0 = 0xfa2561cdf44ac398ULL;
+ uint16_t z = 0, temp;
+ uint16_t k[32], eff_k[32], xleft[33], xright[33], fxleft[32];
+
+ for (int i = 3; i >= 0; i--) {
+ k[i] = key & 0xffff;
+ key >>= 16;
+ }
+ xleft[0] = x & 0xffff;
+ xright[0] = (x >> 16) & 0xffff;
+
+ for (int i = 0; i < 28; i++) {
+ z = (z0 >> (63 - i)) & 1;
+ temp = ror16(k[i + 3], 3) ^ k[i + 1];
+ k[i + 4] = c ^ z ^ k[i] ^ temp ^ ror16(temp, 1);
+ }
+
+ for (int i = 0; i < 8; i++) {
+ eff_k[4 * i + 0] = k[4 * i + ((0 + lane) % 4)];
+ eff_k[4 * i + 1] = k[4 * i + ((1 + lane) % 4)];
+ eff_k[4 * i + 2] = k[4 * i + ((2 + lane) % 4)];
+ eff_k[4 * i + 3] = k[4 * i + ((3 + lane) % 4)];
+ }
+
+ for (int i = 0; i < 32; i++) {
+ fxleft[i] = (rol16(xleft[i], 1) &
+ rol16(xleft[i], 8)) ^ rol16(xleft[i], 2);
+ xleft[i + 1] = xright[i] ^ fxleft[i] ^ eff_k[i];
+ xright[i + 1] = xleft[i];
+ }
+
+ return (((uint32_t)xright[32]) << 16) | xleft[32];
+}
+
+static uint64_t hash_digest(uint64_t ra, uint64_t rb, uint64_t key)
+{
+ uint64_t stage0_h = 0ULL, stage0_l = 0ULL;
+ uint64_t stage1_h, stage1_l;
+
+ for (int i = 0; i < 4; i++) {
+ stage0_h |= ror64(rb & 0xff, 8 * (2 * i + 1));
+ stage0_h |= ((ra >> 32) & 0xff) << (8 * 2 * i);
+ stage0_l |= ror64((rb >> 32) & 0xff, 8 * (2 * i + 1));
+ stage0_l |= (ra & 0xff) << (8 * 2 * i);
+ rb >>= 8;
+ ra >>= 8;
+ }
+
+ stage1_h = (uint64_t)helper_SIMON_LIKE_32_64(stage0_h >> 32, key, 0) << 32;
+ stage1_h |= helper_SIMON_LIKE_32_64(stage0_h, key, 1);
+ stage1_l = (uint64_t)helper_SIMON_LIKE_32_64(stage0_l >> 32, key, 2) << 32;
+ stage1_l |= helper_SIMON_LIKE_32_64(stage0_l, key, 3);
+
+ return stage1_h ^ stage1_l;
+}
+
+#include "qemu/guest-random.h"
+
+#define HELPER_HASH(op, key, store) \
+void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
+ target_ulong rb) \
+{ \
+ uint64_t calculated_hash = hash_digest(ra, rb, key), loaded_hash; \
+ \
+ if (store) { \
+ cpu_stq_data_ra(env, ea, calculated_hash, GETPC()); \
+ } else { \
+ loaded_hash = cpu_ldq_data_ra(env, ea, GETPC()); \
+ if (loaded_hash != calculated_hash) { \
+ /* hashes don't match, trap */ \
+ raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, \
+ POWERPC_EXCP_TRAP, GETPC()); \
+ } \
+ } \
+}
+
+HELPER_HASH(HASHST, env->spr[SPR_HASHKEYR], true)
+HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false)
+
#if !defined(CONFIG_USER_ONLY)
#ifdef CONFIG_TCG
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 159b352f6e..5817af632b 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -4,6 +4,8 @@ DEF_HELPER_FLAGS_4(tw, TCG_CALL_NO_WG, void, env, tl, tl, i32)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_4(td, TCG_CALL_NO_WG, void, env, tl, tl, i32)
#endif
+DEF_HELPER_4(HASHST, void, env, tl, tl, tl)
+DEF_HELPER_4(HASHCHK, void, env, tl, tl, tl)
#if !defined(CONFIG_USER_ONLY)
DEF_HELPER_2(store_msr, void, env, tl)
DEF_HELPER_1(rfi, void, env)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index eb41efc100..544514565c 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -172,6 +172,9 @@
@X_TSX ...... ..... ra:5 rb:5 .......... . &X rt=%x_rt_tsx
@X_TSXP ...... ..... ra:5 rb:5 .......... . &X rt=%rt_tsxp
+%x_dw 0:1 21:5 !function=dw_compose_ea
+@X_DW ...... ..... ra:5 rb:5 .......... . &X rt=%x_dw
+
&X_frtp_vrb frtp vrb
@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp
@@ -323,6 +326,11 @@ CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
PDEPD 011111 ..... ..... ..... 0010011100 - @X
PEXTD 011111 ..... ..... ..... 0010111100 - @X
+# Fixed-Point Hash Instructions
+
+HASHST 011111 ..... ..... ..... 1011010010 . @X_DW
+HASHCHK 011111 ..... ..... ..... 1011110010 . @X_DW
+
## BCD Assist
ADDG6S 011111 ..... ..... ..... - 001001010 - @X
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5a18ee577f..3bdd3e6e3e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6394,6 +6394,11 @@ static int times_16(DisasContext *ctx, int x)
return x * 16;
}
+static int64_t dw_compose_ea(DisasContext *ctx, int x)
+{
+ return deposit64(0xfffffffffffffe00, 3, 6, x);
+}
+
/*
* Helpers for trans_* functions to check for specific insns flags.
* Use token pasting to ensure that we use the proper flag with the
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index db14d3bebc..41c06de8a2 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -540,3 +540,35 @@ static bool trans_CBCDTD(DisasContext *ctx, arg_X_sa *a)
gen_helper_CBCDTD(cpu_gpr[a->ra], cpu_gpr[a->rs]);
return true;
}
+
+static bool do_hash(DisasContext *ctx, arg_X *a, bool priv,
+ void (*helper)(TCGv_ptr, TCGv, TCGv, TCGv))
+{
+ TCGv ea;
+
+ if (!(ctx->insns_flags2 & PPC2_ISA310)) {
+ /* if version is before v3.1, this operation is a nop */
+ return true;
+ }
+
+ if (priv) {
+ /* if instruction is privileged but the context is in user space */
+ REQUIRE_SV(ctx);
+ }
+
+ if (unlikely(a->ra == 0)) {
+ /* if RA=0, the instruction form is invalid */
+ gen_invalid(ctx);
+ return true;
+ }
+
+ ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->rt));
+ helper(cpu_env, ea, cpu_gpr[a->ra], cpu_gpr[a->rb]);
+
+ tcg_temp_free(ea);
+
+ return true;
+}
+
+TRANS(HASHST, do_hash, false, gen_helper_HASHST)
+TRANS(HASHCHK, do_hash, false, gen_helper_HASHCHK)
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v4 2/3] target/ppc: Implement hashst and hashchk
2022-07-15 20:54 ` [PATCH v4 2/3] target/ppc: Implement hashst and hashchk Víctor Colombo
@ 2022-07-18 18:23 ` Lucas Mateus Martins Araujo e Castro
0 siblings, 0 replies; 8+ messages in thread
From: Lucas Mateus Martins Araujo e Castro @ 2022-07-18 18:23 UTC (permalink / raw)
To: Víctor Colombo, qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, cohuck,
farosas
[-- Attachment #1: Type: text/plain, Size: 8738 bytes --]
On 15/07/2022 17:54, Víctor Colombo wrote:
> Implementation for instructions hashst and hashchk, which were added
> in Power ISA 3.1B.
>
> It was decided to implement the hash algorithm from ground up in this
> patch exactly as described in Power ISA.
>
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
> ---
> target/ppc/excp_helper.c | 82 ++++++++++++++++++++++
> target/ppc/helper.h | 2 +
> target/ppc/insn32.decode | 8 +++
> target/ppc/translate.c | 5 ++
> target/ppc/translate/fixedpoint-impl.c.inc | 32 +++++++++
> 5 files changed, 129 insertions(+)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index cb752b184a..fa5a737e22 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -2174,6 +2174,88 @@ void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
> #endif
> #endif
>
> +static uint32_t helper_SIMON_LIKE_32_64(uint32_t x, uint64_t key, uint32_t lane)
> +{
> + const uint16_t c = 0xfffc;
> + const uint64_t z0 = 0xfa2561cdf44ac398ULL;
> + uint16_t z = 0, temp;
> + uint16_t k[32], eff_k[32], xleft[33], xright[33], fxleft[32];
> +
> + for (int i = 3; i >= 0; i--) {
> + k[i] = key & 0xffff;
> + key >>= 16;
> + }
> + xleft[0] = x & 0xffff;
> + xright[0] = (x >> 16) & 0xffff;
> +
> + for (int i = 0; i < 28; i++) {
> + z = (z0 >> (63 - i)) & 1;
> + temp = ror16(k[i + 3], 3) ^ k[i + 1];
> + k[i + 4] = c ^ z ^ k[i] ^ temp ^ ror16(temp, 1);
> + }
> +
> + for (int i = 0; i < 8; i++) {
> + eff_k[4 * i + 0] = k[4 * i + ((0 + lane) % 4)];
> + eff_k[4 * i + 1] = k[4 * i + ((1 + lane) % 4)];
> + eff_k[4 * i + 2] = k[4 * i + ((2 + lane) % 4)];
> + eff_k[4 * i + 3] = k[4 * i + ((3 + lane) % 4)];
> + }
> +
> + for (int i = 0; i < 32; i++) {
> + fxleft[i] = (rol16(xleft[i], 1) &
> + rol16(xleft[i], 8)) ^ rol16(xleft[i], 2);
> + xleft[i + 1] = xright[i] ^ fxleft[i] ^ eff_k[i];
> + xright[i + 1] = xleft[i];
> + }
> +
> + return (((uint32_t)xright[32]) << 16) | xleft[32];
> +}
> +
> +static uint64_t hash_digest(uint64_t ra, uint64_t rb, uint64_t key)
> +{
> + uint64_t stage0_h = 0ULL, stage0_l = 0ULL;
> + uint64_t stage1_h, stage1_l;
> +
> + for (int i = 0; i < 4; i++) {
> + stage0_h |= ror64(rb & 0xff, 8 * (2 * i + 1));
> + stage0_h |= ((ra >> 32) & 0xff) << (8 * 2 * i);
> + stage0_l |= ror64((rb >> 32) & 0xff, 8 * (2 * i + 1));
> + stage0_l |= (ra & 0xff) << (8 * 2 * i);
> + rb >>= 8;
> + ra >>= 8;
> + }
> +
> + stage1_h = (uint64_t)helper_SIMON_LIKE_32_64(stage0_h >> 32, key, 0) << 32;
> + stage1_h |= helper_SIMON_LIKE_32_64(stage0_h, key, 1);
> + stage1_l = (uint64_t)helper_SIMON_LIKE_32_64(stage0_l >> 32, key, 2) << 32;
> + stage1_l |= helper_SIMON_LIKE_32_64(stage0_l, key, 3);
> +
> + return stage1_h ^ stage1_l;
> +}
> +
> +#include "qemu/guest-random.h"
> +
> +#define HELPER_HASH(op, key, store) \
> +void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
> + target_ulong rb) \
> +{ \
> + uint64_t calculated_hash = hash_digest(ra, rb, key), loaded_hash; \
> + \
> + if (store) { \
> + cpu_stq_data_ra(env, ea, calculated_hash, GETPC()); \
> + } else { \
> + loaded_hash = cpu_ldq_data_ra(env, ea, GETPC()); \
> + if (loaded_hash != calculated_hash) { \
> + /* hashes don't match, trap */ \
> + raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, \
> + POWERPC_EXCP_TRAP, GETPC()); \
> + } \
> + } \
> +}
Maybe this macro could be 2 separate helpers so it's easier to debug.
Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br>
> +
> +HELPER_HASH(HASHST, env->spr[SPR_HASHKEYR], true)
> +HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false)
> +
> #if !defined(CONFIG_USER_ONLY)
>
> #ifdef CONFIG_TCG
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 159b352f6e..5817af632b 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -4,6 +4,8 @@ DEF_HELPER_FLAGS_4(tw, TCG_CALL_NO_WG, void, env, tl, tl, i32)
> #if defined(TARGET_PPC64)
> DEF_HELPER_FLAGS_4(td, TCG_CALL_NO_WG, void, env, tl, tl, i32)
> #endif
> +DEF_HELPER_4(HASHST, void, env, tl, tl, tl)
> +DEF_HELPER_4(HASHCHK, void, env, tl, tl, tl)
> #if !defined(CONFIG_USER_ONLY)
> DEF_HELPER_2(store_msr, void, env, tl)
> DEF_HELPER_1(rfi, void, env)
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index eb41efc100..544514565c 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -172,6 +172,9 @@
> @X_TSX ...... ..... ra:5 rb:5 .......... . &X rt=%x_rt_tsx
> @X_TSXP ...... ..... ra:5 rb:5 .......... . &X rt=%rt_tsxp
>
> +%x_dw 0:1 21:5 !function=dw_compose_ea
> +@X_DW ...... ..... ra:5 rb:5 .......... . &X rt=%x_dw
> +
> &X_frtp_vrb frtp vrb
> @X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp
>
> @@ -323,6 +326,11 @@ CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
> PDEPD 011111 ..... ..... ..... 0010011100 - @X
> PEXTD 011111 ..... ..... ..... 0010111100 - @X
>
> +# Fixed-Point Hash Instructions
> +
> +HASHST 011111 ..... ..... ..... 1011010010 . @X_DW
> +HASHCHK 011111 ..... ..... ..... 1011110010 . @X_DW
> +
> ## BCD Assist
>
> ADDG6S 011111 ..... ..... ..... - 001001010 - @X
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 5a18ee577f..3bdd3e6e3e 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -6394,6 +6394,11 @@ static int times_16(DisasContext *ctx, int x)
> return x * 16;
> }
>
> +static int64_t dw_compose_ea(DisasContext *ctx, int x)
> +{
> + return deposit64(0xfffffffffffffe00, 3, 6, x);
> +}
> +
> /*
> * Helpers for trans_* functions to check for specific insns flags.
> * Use token pasting to ensure that we use the proper flag with the
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index db14d3bebc..41c06de8a2 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -540,3 +540,35 @@ static bool trans_CBCDTD(DisasContext *ctx, arg_X_sa *a)
> gen_helper_CBCDTD(cpu_gpr[a->ra], cpu_gpr[a->rs]);
> return true;
> }
> +
> +static bool do_hash(DisasContext *ctx, arg_X *a, bool priv,
> + void (*helper)(TCGv_ptr, TCGv, TCGv, TCGv))
> +{
> + TCGv ea;
> +
> + if (!(ctx->insns_flags2 & PPC2_ISA310)) {
> + /* if version is before v3.1, this operation is a nop */
> + return true;
> + }
> +
> + if (priv) {
> + /* if instruction is privileged but the context is in user space */
> + REQUIRE_SV(ctx);
> + }
> +
> + if (unlikely(a->ra == 0)) {
> + /* if RA=0, the instruction form is invalid */
> + gen_invalid(ctx);
> + return true;
> + }
> +
> + ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->rt));
> + helper(cpu_env, ea, cpu_gpr[a->ra], cpu_gpr[a->rb]);
> +
> + tcg_temp_free(ea);
> +
> + return true;
> +}
> +
> +TRANS(HASHST, do_hash, false, gen_helper_HASHST)
> +TRANS(HASHCHK, do_hash, false, gen_helper_HASHCHK)
> --
> 2.25.1
>
>
--
Lucas Mateus M. Araujo e Castro
Instituto de Pesquisas ELDORADO
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v4 3/3] target/ppc: Implement hashstp and hashchkp
2022-07-15 20:54 [PATCH v4 0/3] Implement Power ISA 3.1B hash insns Víctor Colombo
2022-07-15 20:54 ` [PATCH v4 1/3] target/ppc: Add HASHKEYR and HASHPKEYR SPRs Víctor Colombo
2022-07-15 20:54 ` [PATCH v4 2/3] target/ppc: Implement hashst and hashchk Víctor Colombo
@ 2022-07-15 20:54 ` Víctor Colombo
2022-07-18 18:23 ` Lucas Mateus Martins Araujo e Castro
2022-09-06 18:44 ` [PATCH v4 0/3] Implement Power ISA 3.1B hash insns Daniel Henrique Barboza
3 siblings, 1 reply; 8+ messages in thread
From: Víctor Colombo @ 2022-07-15 20:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, victor.colombo,
cohuck, farosas
Implementation for instructions hashstp and hashchkp, the privileged
versions of hashst and hashchk, which were added in Power ISA 3.1B.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/excp_helper.c | 2 ++
target/ppc/helper.h | 2 ++
target/ppc/insn32.decode | 2 ++
target/ppc/translate/fixedpoint-impl.c.inc | 2 ++
4 files changed, 8 insertions(+)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index fa5a737e22..847eff9213 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -2255,6 +2255,8 @@ void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
HELPER_HASH(HASHST, env->spr[SPR_HASHKEYR], true)
HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false)
+HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true)
+HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false)
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 5817af632b..122b2e9359 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -6,6 +6,8 @@ DEF_HELPER_FLAGS_4(td, TCG_CALL_NO_WG, void, env, tl, tl, i32)
#endif
DEF_HELPER_4(HASHST, void, env, tl, tl, tl)
DEF_HELPER_4(HASHCHK, void, env, tl, tl, tl)
+DEF_HELPER_4(HASHSTP, void, env, tl, tl, tl)
+DEF_HELPER_4(HASHCHKP, void, env, tl, tl, tl)
#if !defined(CONFIG_USER_ONLY)
DEF_HELPER_2(store_msr, void, env, tl)
DEF_HELPER_1(rfi, void, env)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 544514565c..da08960fca 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -330,6 +330,8 @@ PEXTD 011111 ..... ..... ..... 0010111100 - @X
HASHST 011111 ..... ..... ..... 1011010010 . @X_DW
HASHCHK 011111 ..... ..... ..... 1011110010 . @X_DW
+HASHSTP 011111 ..... ..... ..... 1010010010 . @X_DW
+HASHCHKP 011111 ..... ..... ..... 1010110010 . @X_DW
## BCD Assist
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 41c06de8a2..1ba56cbed5 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -572,3 +572,5 @@ static bool do_hash(DisasContext *ctx, arg_X *a, bool priv,
TRANS(HASHST, do_hash, false, gen_helper_HASHST)
TRANS(HASHCHK, do_hash, false, gen_helper_HASHCHK)
+TRANS(HASHSTP, do_hash, true, gen_helper_HASHSTP)
+TRANS(HASHCHKP, do_hash, true, gen_helper_HASHCHKP)
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v4 3/3] target/ppc: Implement hashstp and hashchkp
2022-07-15 20:54 ` [PATCH v4 3/3] target/ppc: Implement hashstp and hashchkp Víctor Colombo
@ 2022-07-18 18:23 ` Lucas Mateus Martins Araujo e Castro
0 siblings, 0 replies; 8+ messages in thread
From: Lucas Mateus Martins Araujo e Castro @ 2022-07-18 18:23 UTC (permalink / raw)
To: Víctor Colombo, qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, cohuck,
farosas
[-- Attachment #1: Type: text/plain, Size: 3146 bytes --]
Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br>
On 15/07/2022 17:54, Víctor Colombo wrote:
> Implementation for instructions hashstp and hashchkp, the privileged
> versions of hashst and hashchk, which were added in Power ISA 3.1B.
>
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
> ---
> target/ppc/excp_helper.c | 2 ++
> target/ppc/helper.h | 2 ++
> target/ppc/insn32.decode | 2 ++
> target/ppc/translate/fixedpoint-impl.c.inc | 2 ++
> 4 files changed, 8 insertions(+)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index fa5a737e22..847eff9213 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -2255,6 +2255,8 @@ void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
>
> HELPER_HASH(HASHST, env->spr[SPR_HASHKEYR], true)
> HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false)
> +HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true)
> +HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false)
>
> #if !defined(CONFIG_USER_ONLY)
>
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 5817af632b..122b2e9359 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -6,6 +6,8 @@ DEF_HELPER_FLAGS_4(td, TCG_CALL_NO_WG, void, env, tl, tl, i32)
> #endif
> DEF_HELPER_4(HASHST, void, env, tl, tl, tl)
> DEF_HELPER_4(HASHCHK, void, env, tl, tl, tl)
> +DEF_HELPER_4(HASHSTP, void, env, tl, tl, tl)
> +DEF_HELPER_4(HASHCHKP, void, env, tl, tl, tl)
> #if !defined(CONFIG_USER_ONLY)
> DEF_HELPER_2(store_msr, void, env, tl)
> DEF_HELPER_1(rfi, void, env)
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 544514565c..da08960fca 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -330,6 +330,8 @@ PEXTD 011111 ..... ..... ..... 0010111100 - @X
>
> HASHST 011111 ..... ..... ..... 1011010010 . @X_DW
> HASHCHK 011111 ..... ..... ..... 1011110010 . @X_DW
> +HASHSTP 011111 ..... ..... ..... 1010010010 . @X_DW
> +HASHCHKP 011111 ..... ..... ..... 1010110010 . @X_DW
>
> ## BCD Assist
>
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index 41c06de8a2..1ba56cbed5 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -572,3 +572,5 @@ static bool do_hash(DisasContext *ctx, arg_X *a, bool priv,
>
> TRANS(HASHST, do_hash, false, gen_helper_HASHST)
> TRANS(HASHCHK, do_hash, false, gen_helper_HASHCHK)
> +TRANS(HASHSTP, do_hash, true, gen_helper_HASHSTP)
> +TRANS(HASHCHKP, do_hash, true, gen_helper_HASHCHKP)
> --
> 2.25.1
>
>
--
Lucas Mateus M. Araujo e Castro
Instituto de Pesquisas ELDORADO
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 0/3] Implement Power ISA 3.1B hash insns
2022-07-15 20:54 [PATCH v4 0/3] Implement Power ISA 3.1B hash insns Víctor Colombo
` (2 preceding siblings ...)
2022-07-15 20:54 ` [PATCH v4 3/3] target/ppc: Implement hashstp and hashchkp Víctor Colombo
@ 2022-09-06 18:44 ` Daniel Henrique Barboza
3 siblings, 0 replies; 8+ messages in thread
From: Daniel Henrique Barboza @ 2022-09-06 18:44 UTC (permalink / raw)
To: Víctor Colombo, qemu-devel, qemu-ppc
Cc: clg, david, groug, richard.henderson, cohuck, farosas
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 7/15/22 17:54, Víctor Colombo wrote:
> This patch series implements the 4 instructions added in Power ISA
> 3.1B:
>
> - hashchk
> - hashst
> - hashchkp
> - hashstp
>
> It's built on top of ppc-next. Working branch for ease of use can be
> found here:
> https://github.com/PPC64/qemu/tree/vccolombo-hash-to-send-v4
>
> What do you think about the choice to implement the hash algorithm
> from the ground up, following the SIMON-like algorithm presented in
> Power ISA? IIUC, this algorithm is not the same as the original[1].
> Other options would be to use other algorithm already implemented
> in QEMU, or even make this instruction a nop for all Power versions.
>
> v1->v2:
> - Split the patch in 2
> - Rebase to master
>
> v2->v3:
> - Split patches in 3
> - the new patch (patch 1) is separating the kvm header
> changes [Cornelia]
>
> v3->v4:
> - Remove Patch 1 (linux-headers/asm-powerpc/kvm.h:
> Add HASHKEYR and HASHPKEYR in headers)
> - Daniel recommended drop the kvm part:
> https://lists.nongnu.org/archive/html/qemu-ppc/2022-07/msg00213.html
> - Substitute Patch 1 with a separated patch setting up the registers
> for TCG only. Also, now setup it with a random value in linux-user.
> - Change the registers naming:
> - SPR_POWER_HASHKEYR -> SPR_HASHKEYR
> - Drop RFC tag
>
> [1] https://eprint.iacr.org/2013/404.pdf
>
> Víctor Colombo (3):
> target/ppc: Add HASHKEYR and HASHPKEYR SPRs
> target/ppc: Implement hashst and hashchk
> target/ppc: Implement hashstp and hashchkp
>
> target/ppc/cpu.h | 2 +
> target/ppc/cpu_init.c | 28 ++++++++
> target/ppc/excp_helper.c | 84 ++++++++++++++++++++++
> target/ppc/helper.h | 4 ++
> target/ppc/insn32.decode | 10 +++
> target/ppc/translate.c | 5 ++
> target/ppc/translate/fixedpoint-impl.c.inc | 34 +++++++++
> 7 files changed, 167 insertions(+)
>
^ permalink raw reply [flat|nested] 8+ messages in thread