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Fri, 08 Aug 2025 10:14:46 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-241e8ab3da8sm213752765ad.175.2025.08.08.10.14.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Aug 2025 10:14:45 -0700 (PDT) Message-ID: <96a27883-e02e-4d76-9dde-41ae1a19e0c3@linaro.org> Date: Fri, 8 Aug 2025 10:14:44 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] gdbstub/aarch64: add CurrentEL register Content-Language: en-US To: Peter Maydell Cc: Manos Pitsidianakis , qemu-devel@nongnu.org, =?UTF-8?Q?Alex_Benn=C3=A9e?= , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Gustavo Romero , Richard Henderson , qemu-arm@nongnu.org References: <20250808-gdbstub-aarch64-pstate-regs-v1-0-14ba70be1b3d@linaro.org> <20250808-gdbstub-aarch64-pstate-regs-v1-1-14ba70be1b3d@linaro.org> <6190716c-09da-4abe-94e5-2b713855f0e9@linaro.org> From: Pierrick Bouvier In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/8/25 9:14 AM, Peter Maydell wrote: > On Fri, 8 Aug 2025 at 17:11, Pierrick Bouvier > wrote: >> >> On 8/8/25 5:26 AM, Manos Pitsidianakis wrote: >>> On Fri, Aug 8, 2025 at 3:21 PM Peter Maydell wrote: >>>> >>>> On Fri, 8 Aug 2025 at 12:30, Manos Pitsidianakis >>>> wrote: >>>> The debugger already has this information in the 'cpsr' >>>> register, so it could implement convenience views of >>>> the subfields itself if it liked. >>> >>> Yep, but consider: it is a register, architecturally, so it's nice to >>> include it for consistency. It's redundant only because gdb has cpsr >>> which is not a register. So this is about more about being technically >>> correct than correcting an actual problem. >>> >> >> I agree with Manos on this. >> As mentioned on a previous thread, cpsr is not even supposed to exist >> for aarch64. So adding architecturally defined registers, even if data >> is redundant with cpsr, should not be a problem. >> I'm sure gdb folks can understand this too. > > I'm not saying this is the wrong way to represent this. > I'm just saying we're not the only gdbstub in the world, > and it would be nice to have a wider discussion than just > QEMU folks so we are consistent about how we represent > PSTATE (including what we want to do about the new > bits that appear in the high 32 bits of an SPSR), before > we commit to any particular direction. > Considering we have our own set of gdb xml, is that really important to agree on pstate layout before we simply make those registers visible on our side? The new registers added in this series on gdb/kgdb side at the moment, so we don't really break anything. I agree it would be good to see this on gdb side, but my point is that we are not necessarily stuck and we can make this visible without waiting two releases. As well, it would be a good motivation to add this on gdb showing QEMU already exposes this. > -- PMM