* [PATCH] target/mips: tcg: detect out-of-bounds accesses to cpu_gpr and cpu_gpr_hi
@ 2023-04-03 17:29 Paolo Bonzini
2023-04-03 18:21 ` Richard Henderson
0 siblings, 1 reply; 2+ messages in thread
From: Paolo Bonzini @ 2023-04-03 17:29 UTC (permalink / raw)
To: qemu-devel; +Cc: philmd
In some cases (for example gen_compute_branch_nm in
nanomips_translate.c.inc) registers can be unused
on some paths and a negative value is passed in that case:
gen_compute_branch_nm(ctx, OPC_BPOSGE32, 4, -1, -2,
imm << 1);
To avoid an out of bounds access in those cases, introduce
assertions.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/mips/tcg/translate.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 1fb4ef712729..999fbb7cc1c0 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1223,6 +1223,7 @@ static const char regnames_LO[][4] = {
/* General purpose registers moves. */
void gen_load_gpr(TCGv t, int reg)
{
+ assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr));
if (reg == 0) {
tcg_gen_movi_tl(t, 0);
} else {
@@ -1232,6 +1233,7 @@ void gen_load_gpr(TCGv t, int reg)
void gen_store_gpr(TCGv t, int reg)
{
+ assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr));
if (reg != 0) {
tcg_gen_mov_tl(cpu_gpr[reg], t);
}
@@ -1240,6 +1242,7 @@ void gen_store_gpr(TCGv t, int reg)
#if defined(TARGET_MIPS64)
void gen_load_gpr_hi(TCGv_i64 t, int reg)
{
+ assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr_hi));
if (reg == 0) {
tcg_gen_movi_i64(t, 0);
} else {
@@ -1249,6 +1252,7 @@ void gen_load_gpr_hi(TCGv_i64 t, int reg)
void gen_store_gpr_hi(TCGv_i64 t, int reg)
{
+ assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr_hi));
if (reg != 0) {
tcg_gen_mov_i64(cpu_gpr_hi[reg], t);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] target/mips: tcg: detect out-of-bounds accesses to cpu_gpr and cpu_gpr_hi
2023-04-03 17:29 [PATCH] target/mips: tcg: detect out-of-bounds accesses to cpu_gpr and cpu_gpr_hi Paolo Bonzini
@ 2023-04-03 18:21 ` Richard Henderson
0 siblings, 0 replies; 2+ messages in thread
From: Richard Henderson @ 2023-04-03 18:21 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel; +Cc: philmd
On 4/3/23 10:29, Paolo Bonzini wrote:
> In some cases (for example gen_compute_branch_nm in
> nanomips_translate.c.inc) registers can be unused
> on some paths and a negative value is passed in that case:
>
> gen_compute_branch_nm(ctx, OPC_BPOSGE32, 4, -1, -2,
> imm << 1);
>
> To avoid an out of bounds access in those cases, introduce
> assertions.
>
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
> target/mips/tcg/translate.c | 4 ++++
> 1 file changed, 4 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-04-03 17:29 [PATCH] target/mips: tcg: detect out-of-bounds accesses to cpu_gpr and cpu_gpr_hi Paolo Bonzini
2023-04-03 18:21 ` Richard Henderson
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