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Sat, 25 Jan 2025 09:25:58 -0800 (PST) Received: from [192.168.74.94] ([50.200.230.211]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-ac48f897f8dsm3439095a12.22.2025.01.25.09.25.58 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 25 Jan 2025 09:25:58 -0800 (PST) Message-ID: <97144c39-9a84-4574-bff5-3a6d3b09b83e@linaro.org> Date: Sat, 25 Jan 2025 09:25:56 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 28/76] target/arm: Implement FPCR.FIZ handling To: qemu-devel@nongnu.org References: <20250124162836.2332150-1-peter.maydell@linaro.org> <20250124162836.2332150-29-peter.maydell@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20250124162836.2332150-29-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/24/25 08:27, Peter Maydell wrote: > Part of FEAT_AFP is the new control bit FPCR.FIZ. This bit affects > flushing of single and double precision denormal inputs to zero for > AArch64 floating point instructions. (For half-precision, the > existing FPCR.FZ16 control remains the only one.) > > FPCR.FIZ differs from FPCR.FZ in that if we flush an input denormal > only because of FPCR.FIZ then we should *not* set the cumulative > exception bit FPSR.IDC. > > FEAT_AFP also defines that in AArch64 the existing FPCR.FZ only > applies when FPCR.AH is 0. > > We can implement this by setting the "flush inputs to zero" state > appropriately when FPCR is written, and by not reflecting the > float_flag_input_denormal status flag into FPSR reads when it is the > result only of FPSR.FIZ. > > Signed-off-by: Peter Maydell > --- > target/arm/vfp_helper.c | 58 ++++++++++++++++++++++++++++++++++------- > 1 file changed, 48 insertions(+), 10 deletions(-) > > diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c > index 8c79ab4fc8a..5a0b389f7a3 100644 > --- a/target/arm/vfp_helper.c > +++ b/target/arm/vfp_helper.c > @@ -61,19 +61,29 @@ static inline uint32_t vfp_exceptbits_from_host(int host_bits) > > static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) > { > - uint32_t i = 0; > + uint32_t a32_flags = 0, a64_flags = 0; > > - i |= get_float_exception_flags(&env->vfp.fp_status_a32); > - i |= get_float_exception_flags(&env->vfp.fp_status_a64); > - i |= get_float_exception_flags(&env->vfp.standard_fp_status); > + a32_flags |= get_float_exception_flags(&env->vfp.fp_status_a32); > + a32_flags |= get_float_exception_flags(&env->vfp.standard_fp_status); > /* FZ16 does not generate an input denormal exception. */ > - i |= (get_float_exception_flags(&env->vfp.fp_status_f16_a32) > + a32_flags |= (get_float_exception_flags(&env->vfp.fp_status_f16_a32) > & ~float_flag_input_denormal_flushed); > - i |= (get_float_exception_flags(&env->vfp.fp_status_f16_a64) > + a32_flags |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16) > & ~float_flag_input_denormal_flushed); > - i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16) > + > + a64_flags |= get_float_exception_flags(&env->vfp.fp_status_a64); > + a64_flags |= (get_float_exception_flags(&env->vfp.fp_status_f16_a64) > & ~float_flag_input_denormal_flushed); > - return vfp_exceptbits_from_host(i); > + /* > + * Flushing an input denormal only because FPCR.FIZ == 1 does > + * not set FPSR.IDC. So squash it unless (FPCR.AH == 0 && FPCR.FZ == 1). > + * We only do this for the a64 flags because FIZ has no effect > + * on AArch32 even if it is set. > + */ > + if ((env->vfp.fpcr & (FPCR_FZ | FPCR_AH)) != FPCR_FZ) { > + a64_flags &= ~float_flag_input_denormal_flushed; > + } It might be worth pointing to FPUnpackBase pseudocode to say if both FZ and FIZ set, FZ takes precedence for setting IDC. Anyway, Reviewed-by: Richard Henderson r~