[Qemu-devel] [PATCH 1/2][sparc64] Fix vector interrupt handling

[Qemu-devel] [PATCH 1/2][sparc64] Fix vector interrupt handling

[Artyom Tarasenko]

Don't produce stray irq 5, don't overwrite ivec_data if still busy with
processing of the previous interrupt.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
---
 hw/sun4u.c |   29 ++++++++++++++++-------------
 1 files changed, 16 insertions(+), 13 deletions(-)

diff --git a/hw/sun4u.c b/hw/sun4u.c
index 1d67691..9d28194 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -315,19 +315,22 @@ static void cpu_set_ivec_irq(void *opaque, int irq, int level)
     CPUSPARCState *env = opaque;
 
     if (level) {
-        CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
-        env->interrupt_index = TT_IVEC;
-        env->pil_in |= 1 << 5;
-        env->ivec_status |= 0x20;
-        env->ivec_data[0] = (0x1f << 6) | irq;
-        env->ivec_data[1] = 0;
-        env->ivec_data[2] = 0;
-        cpu_interrupt(env, CPU_INTERRUPT_HARD);
-      } else {
-        CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
-        env->pil_in &= ~(1 << 5);
-        env->ivec_status &= ~0x20;
-        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+        if (!(env->ivec_status & 0x20)) {
+            CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
+            env->halted = 0;
+            env->interrupt_index = TT_IVEC;
+            env->ivec_status |= 0x20;
+            env->ivec_data[0] = (0x1f << 6) | irq;
+            env->ivec_data[1] = 0;
+            env->ivec_data[2] = 0;
+            cpu_interrupt(env, CPU_INTERRUPT_HARD);
+        }
+    } else {
+        if (env->ivec_status & 0x20) {
+            CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
+            env->ivec_status &= ~0x20;
+            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+        }
     }
 }
 
-- 
1.7.3.4

[Qemu-devel] [PATCH 2/2][sparc64] Improve interrupt handling priority

[Artyom Tarasenko]

The vector interrupt has higher priority than interrupt_level_n.
Also check only interrupt_level_n concurency when TL > 0, the traps of
other types may be nested.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
---
 hw/sun4u.c |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/hw/sun4u.c b/hw/sun4u.c
index 9d28194..e6b18f7 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -254,6 +254,10 @@ void cpu_check_irqs(CPUSPARCState *env)
     uint32_t pil = env->pil_in |
                   (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
 
+    /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
+    if (env->ivec_status & 0x20) {
+        return;
+    }
     /* check if TM or SM in SOFTINT are set
        setting these also causes interrupt 14 */
     if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
@@ -281,7 +285,8 @@ void cpu_check_irqs(CPUSPARCState *env)
                 int old_interrupt = env->interrupt_index;
                 int new_interrupt = TT_EXTINT | i;
 
-                if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) {
+                if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
+                  && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
                     CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
                                    "current %x >= pending %x\n",
                                    env->tl, cpu_tsptr(env)->tt, new_interrupt);
-- 
1.7.3.4

Re: [Qemu-devel] [PATCH 1/2][sparc64] Fix vector interrupt handling

[Blue Swirl]

Thanks, applied both.

On Tue, Apr 3, 2012 at 15:49, Artyom Tarasenko <atar4qemu@gmail.com> wrote:
> Don't produce stray irq 5, don't overwrite ivec_data if still busy with
> processing of the previous interrupt.
>
> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
> ---
>  hw/sun4u.c |   29 ++++++++++++++++-------------
>  1 files changed, 16 insertions(+), 13 deletions(-)
>
> diff --git a/hw/sun4u.c b/hw/sun4u.c
> index 1d67691..9d28194 100644
> --- a/hw/sun4u.c
> +++ b/hw/sun4u.c
> @@ -315,19 +315,22 @@ static void cpu_set_ivec_irq(void *opaque, int irq, int level)
>     CPUSPARCState *env = opaque;
>
>     if (level) {
> -        CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
> -        env->interrupt_index = TT_IVEC;
> -        env->pil_in |= 1 << 5;
> -        env->ivec_status |= 0x20;
> -        env->ivec_data[0] = (0x1f << 6) | irq;
> -        env->ivec_data[1] = 0;
> -        env->ivec_data[2] = 0;
> -        cpu_interrupt(env, CPU_INTERRUPT_HARD);
> -      } else {
> -        CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
> -        env->pil_in &= ~(1 << 5);
> -        env->ivec_status &= ~0x20;
> -        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
> +        if (!(env->ivec_status & 0x20)) {
> +            CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
> +            env->halted = 0;
> +            env->interrupt_index = TT_IVEC;
> +            env->ivec_status |= 0x20;
> +            env->ivec_data[0] = (0x1f << 6) | irq;
> +            env->ivec_data[1] = 0;
> +            env->ivec_data[2] = 0;
> +            cpu_interrupt(env, CPU_INTERRUPT_HARD);
> +        }
> +    } else {
> +        if (env->ivec_status & 0x20) {
> +            CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
> +            env->ivec_status &= ~0x20;
> +            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
> +        }
>     }
>  }
>
> --
> 1.7.3.4
>