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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>,
	qemu-devel@nongnu.org, Anton Johansson <anjo@rev.ng>
Subject: Re: [PATCH 09/11] accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
Date: Wed, 12 Feb 2025 08:22:43 +0100	[thread overview]
Message-ID: <9759c6f3-18c7-4693-a2db-8a10fea182c8@linaro.org> (raw)
In-Reply-To: <20250205040341.2056361-10-richard.henderson@linaro.org>

On 5/2/25 05:03, Richard Henderson wrote:
> The declarations use vaddr for size.

Which seems dubious, since TARGET_PAGE_SIZE is int IIUC.

> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   accel/tcg/cputlb.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index 17e2251695..75d075d044 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -1193,7 +1193,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,
>   
>   void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
>                                hwaddr paddr, MemTxAttrs attrs, int prot,
> -                             int mmu_idx, uint64_t size)
> +                             int mmu_idx, vaddr size)
>   {
>       CPUTLBEntryFull full = {
>           .phys_addr = paddr,
> @@ -1208,7 +1208,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
>   
>   void tlb_set_page(CPUState *cpu, vaddr addr,
>                     hwaddr paddr, int prot,
> -                  int mmu_idx, uint64_t size)
> +                  int mmu_idx, vaddr size)
>   {
>       tlb_set_page_with_attrs(cpu, addr, paddr, MEMTXATTRS_UNSPECIFIED,
>                               prot, mmu_idx, size);



  reply	other threads:[~2025-02-12  7:23 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-05  4:03 [PATCH 00/11] tcg: Cleanups after disallowing 64-on-32 Richard Henderson
2025-02-05  4:03 ` [PATCH 01/11] tcg: Drop support for two address registers in gen_ldst Richard Henderson
2025-02-13 14:37   ` Philippe Mathieu-Daudé
2025-02-05  4:03 ` [PATCH 02/11] tcg: Merge INDEX_op_qemu_*_{a32,a64}_* Richard Henderson
2025-02-17 14:22   ` Philippe Mathieu-Daudé
2025-02-05  4:03 ` [PATCH 03/11] tcg/arm: Drop addrhi from prepare_host_addr Richard Henderson
2025-02-17 12:12   ` Philippe Mathieu-Daudé
2025-02-17 16:44     ` Richard Henderson
2025-02-05  4:03 ` [PATCH 04/11] tcg/i386: " Richard Henderson
2025-02-13 14:35   ` Philippe Mathieu-Daudé
2025-02-05  4:03 ` [PATCH 05/11] tcg/mips: " Richard Henderson
2025-02-13 14:33   ` Philippe Mathieu-Daudé
2025-02-05  4:03 ` [PATCH 06/11] tcg/ppc: " Richard Henderson
2025-02-13 14:34   ` Philippe Mathieu-Daudé
2025-02-05  4:03 ` [PATCH 07/11] tcg: Replace addr{lo, hi}_reg with addr_reg in TCGLabelQemuLdst Richard Henderson
2025-02-12  7:14   ` Philippe Mathieu-Daudé
2025-02-05  4:03 ` [PATCH 08/11] plugins: Fix qemu_plugin_read_memory_vaddr parameters Richard Henderson
2025-02-12  7:16   ` Philippe Mathieu-Daudé
2025-02-05  4:03 ` [PATCH 09/11] accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page Richard Henderson
2025-02-12  7:22   ` Philippe Mathieu-Daudé [this message]
2025-02-12 18:21     ` Richard Henderson
2025-02-17  7:32       ` Philippe Mathieu-Daudé
2025-02-05  4:03 ` [PATCH 10/11] include/exec: Change vaddr to uintptr_t Richard Henderson
2025-02-12  7:24   ` Philippe Mathieu-Daudé
2025-02-05  4:03 ` [PATCH 11/11] include/exec: Use uintptr_t in CPUTLBEntry Richard Henderson
2025-02-13 14:29   ` Philippe Mathieu-Daudé
2025-02-15 20:06 ` [PATCH 00/11] tcg: Cleanups after disallowing 64-on-32 Richard Henderson

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