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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id h14sm8293710qth.23.2021.11.02.07.18.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Nov 2021 07:18:40 -0700 (PDT) Subject: Re: [RFC 1/6] target/riscv: rvk: add flag support for Zbk[bcx] To: liweiwei , palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org References: <20211102031128.17296-1-liweiwei@iscas.ac.cn> <20211102031128.17296-2-liweiwei@iscas.ac.cn> From: Richard Henderson Message-ID: <97624133-30f2-fdc4-4f3c-0cc843f0768c@linaro.org> Date: Tue, 2 Nov 2021 10:18:38 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211102031128.17296-2-liweiwei@iscas.ac.cn> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::833; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x833.google.com X-Spam_score_int: -45 X-Spam_score: -4.6 X-Spam_bar: ---- X-Spam_report: (-4.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.549, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, luruibo2000@163.com, lustrew@foxmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/1/21 11:11 PM, liweiwei wrote: > +++ b/target/riscv/cpu.c > @@ -472,15 +472,15 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > error_setg(errp, > "I and E extensions are incompatible"); > return; > - } > + } > > if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { > error_setg(errp, > "Either I or E extension must be set"); > return; > - } > + } > > - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & > + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & > cpu->cfg.ext_a & cpu->cfg.ext_f & > cpu->cfg.ext_d)) { > warn_report("Setting G will also set IMAFD"); This re-indentation should not be happening. > + DEFINE_PROP_BOOL("x-zbkb", RISCVCPU, cfg.ext_zbkb, false), > + DEFINE_PROP_BOOL("x-zbkc", RISCVCPU, cfg.ext_zbkc, false), > + DEFINE_PROP_BOOL("x-zbkx", RISCVCPU, cfg.ext_zbkx, false), The properties cannot be exposed until the end. > bool ext_zbb; > bool ext_zbc; > bool ext_zbs; > + bool ext_zbkb; > + bool ext_zbkc; > + bool ext_zbkx; Better to keep them alphabetical: zbk* < zbs. r~