From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com,
TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Subject: Re: [PATCH v2 13/14] tcg/riscv: Implement vector roti/v/x shi ops
Date: Tue, 3 Sep 2024 08:15:49 -0700 [thread overview]
Message-ID: <97873524-9e47-44c4-b34a-a27e9833b0e1@linaro.org> (raw)
In-Reply-To: <20240830061607.1940-14-zhiwei_liu@linux.alibaba.com>
On 8/29/24 23:16, LIU Zhiwei wrote:
> @@ -2589,6 +2605,69 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
> }
> }
> break;
> + case INDEX_op_shli_vec:
> + if (a2 > 31) {
> + tcg_gen_shls_vec(vece, v0, v1, tcg_constant_i32(a2));
> + } else {
> + vec_gen_3(INDEX_op_rvv_shli_vec, type, vece, tcgv_vec_arg(v0),
> + tcgv_vec_arg(v1), a2);
> + }
> + break;
> + case INDEX_op_shri_vec:
> + if (a2 > 31) {
> + tcg_gen_shrs_vec(vece, v0, v1, tcg_constant_i32(a2));
> + } else {
> + vec_gen_3(INDEX_op_rvv_shri_vec, type, vece, tcgv_vec_arg(v0),
> + tcgv_vec_arg(v1), a2);
> + }
> + break;
> + case INDEX_op_sari_vec:
> + if (a2 > 31) {
> + tcg_gen_sars_vec(vece, v0, v1, tcg_constant_i32(a2));
> + } else {
> + vec_gen_3(INDEX_op_rvv_sari_vec, type, vece, tcgv_vec_arg(v0),
> + tcgv_vec_arg(v1), a2);
> + }
> + break;
> + case INDEX_op_rotli_vec:
> + t1 = tcg_temp_new_vec(type);
> + tcg_gen_shli_vec(vece, t1, v1, a2);
> + tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - a2);
> + tcg_gen_or_vec(vece, v0, v0, t1);
> + tcg_temp_free_vec(t1);
> + break;
> + case INDEX_op_rotls_vec:
> + t1 = tcg_temp_new_vec(type);
> + t2 = tcg_temp_new_i32();
> + tcg_gen_neg_i32(t2, temp_tcgv_i32(arg_temp(a2)));
> + tcg_gen_shrs_vec(vece, v0, v1, t2);
> + tcg_gen_shls_vec(vece, t1, v1, temp_tcgv_i32(arg_temp(a2)));
> + tcg_gen_or_vec(vece, v0, v0, t1);
> + tcg_temp_free_vec(t1);
> + tcg_temp_free_i32(t2);
> + break;
I'm trying to work out how much benefit there is here of expanding these early, as opposed
to simply using TCG_REG_TMP0 when the immediate doesn't fit, or for rotls_vec negation.
> + case INDEX_op_rotlv_vec:
> + v2 = temp_tcgv_vec(arg_temp(a2));
> + t1 = tcg_temp_new_vec(type);
> + tcg_gen_neg_vec(vece, t1, v2);
> + vec_gen_3(INDEX_op_shrv_vec, type, vece, tcgv_vec_arg(t1),
> + tcgv_vec_arg(v1), tcgv_vec_arg(t1));
> + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0),
> + tcgv_vec_arg(v1), tcgv_vec_arg(v2));
> + tcg_gen_or_vec(vece, v0, v0, t1);
> + tcg_temp_free_vec(t1);
> + break;
> + case INDEX_op_rotrv_vec:
> + v2 = temp_tcgv_vec(arg_temp(a2));
> + t1 = tcg_temp_new_vec(type);
> + tcg_gen_neg_vec(vece, t1, v2);
> + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1),
> + tcgv_vec_arg(v1), tcgv_vec_arg(t1));
> + vec_gen_3(INDEX_op_shrv_vec, type, vece, tcgv_vec_arg(v0),
> + tcgv_vec_arg(v1), tcgv_vec_arg(v2));
> + tcg_gen_or_vec(vece, v0, v0, t1);
> + tcg_temp_free_vec(t1);
> + break;
And here we can use TCG_REG_V0 as the temporary, both for negation and shift intermediate.
vrsub_vi V0, a2, 0
vshlv_vv V0, a1, V0
vshrv_vv a0, a1, a2
vor_vv a0, a0, V0
r~
next prev parent reply other threads:[~2024-09-03 15:17 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-30 6:15 [PATCH v2 00/14] tcg/riscv: Add support for vector LIU Zhiwei
2024-08-30 6:15 ` [PATCH v2 01/14] tcg/op-gvec: Fix iteration step in 32-bit operation LIU Zhiwei
2024-08-31 23:59 ` Richard Henderson
2024-08-30 6:15 ` [PATCH v2 02/14] util: Add RISC-V vector extension probe in cpuinfo LIU Zhiwei
2024-09-02 0:12 ` Richard Henderson
2024-08-30 6:15 ` [PATCH v2 03/14] tcg/riscv: Add basic support for vector LIU Zhiwei
2024-09-02 0:28 ` Richard Henderson
2024-08-30 6:15 ` [PATCH v2 04/14] tcg/riscv: Add riscv vset{i}vli support LIU Zhiwei
2024-09-02 1:06 ` Richard Henderson
2024-08-30 6:15 ` [PATCH v2 05/14] tcg/riscv: Implement vector load/store LIU Zhiwei
2024-09-02 1:31 ` Richard Henderson
2024-08-30 6:15 ` [PATCH v2 06/14] tcg/riscv: Implement vector mov/dup{m/i} LIU Zhiwei
2024-09-02 1:36 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 07/14] tcg/riscv: Add support for basic vector opcodes LIU Zhiwei
2024-09-02 1:39 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 08/14] tcg/riscv: Implement vector cmp ops LIU Zhiwei
2024-09-03 6:45 ` Richard Henderson
2024-09-03 14:51 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 09/14] tcg/riscv: Implement vector neg ops LIU Zhiwei
2024-09-03 14:52 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 10/14] tcg/riscv: Implement vector sat/mul ops LIU Zhiwei
2024-09-03 14:52 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 11/14] tcg/riscv: Implement vector min/max ops LIU Zhiwei
2024-09-03 14:53 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 12/14] tcg/riscv: Implement vector shs/v ops LIU Zhiwei
2024-09-03 14:54 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 13/14] tcg/riscv: Implement vector roti/v/x shi ops LIU Zhiwei
2024-09-03 15:15 ` Richard Henderson [this message]
2024-09-04 15:25 ` LIU Zhiwei
2024-09-04 19:05 ` Richard Henderson
2024-09-05 1:40 ` LIU Zhiwei
2024-08-30 6:16 ` [PATCH v2 14/14] tcg/riscv: Enable native vector support for TCG host LIU Zhiwei
2024-09-03 15:02 ` Richard Henderson
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