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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-715edc66743sm7633024b3a.152.2024.09.03.08.15.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Sep 2024 08:15:50 -0700 (PDT) Message-ID: <97873524-9e47-44c4-b34a-a27e9833b0e1@linaro.org> Date: Tue, 3 Sep 2024 08:15:49 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 13/14] tcg/riscv: Implement vector roti/v/x shi ops To: LIU Zhiwei , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng References: <20240830061607.1940-1-zhiwei_liu@linux.alibaba.com> <20240830061607.1940-14-zhiwei_liu@linux.alibaba.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240830061607.1940-14-zhiwei_liu@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/29/24 23:16, LIU Zhiwei wrote: > @@ -2589,6 +2605,69 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, > } > } > break; > + case INDEX_op_shli_vec: > + if (a2 > 31) { > + tcg_gen_shls_vec(vece, v0, v1, tcg_constant_i32(a2)); > + } else { > + vec_gen_3(INDEX_op_rvv_shli_vec, type, vece, tcgv_vec_arg(v0), > + tcgv_vec_arg(v1), a2); > + } > + break; > + case INDEX_op_shri_vec: > + if (a2 > 31) { > + tcg_gen_shrs_vec(vece, v0, v1, tcg_constant_i32(a2)); > + } else { > + vec_gen_3(INDEX_op_rvv_shri_vec, type, vece, tcgv_vec_arg(v0), > + tcgv_vec_arg(v1), a2); > + } > + break; > + case INDEX_op_sari_vec: > + if (a2 > 31) { > + tcg_gen_sars_vec(vece, v0, v1, tcg_constant_i32(a2)); > + } else { > + vec_gen_3(INDEX_op_rvv_sari_vec, type, vece, tcgv_vec_arg(v0), > + tcgv_vec_arg(v1), a2); > + } > + break; > + case INDEX_op_rotli_vec: > + t1 = tcg_temp_new_vec(type); > + tcg_gen_shli_vec(vece, t1, v1, a2); > + tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - a2); > + tcg_gen_or_vec(vece, v0, v0, t1); > + tcg_temp_free_vec(t1); > + break; > + case INDEX_op_rotls_vec: > + t1 = tcg_temp_new_vec(type); > + t2 = tcg_temp_new_i32(); > + tcg_gen_neg_i32(t2, temp_tcgv_i32(arg_temp(a2))); > + tcg_gen_shrs_vec(vece, v0, v1, t2); > + tcg_gen_shls_vec(vece, t1, v1, temp_tcgv_i32(arg_temp(a2))); > + tcg_gen_or_vec(vece, v0, v0, t1); > + tcg_temp_free_vec(t1); > + tcg_temp_free_i32(t2); > + break; I'm trying to work out how much benefit there is here of expanding these early, as opposed to simply using TCG_REG_TMP0 when the immediate doesn't fit, or for rotls_vec negation. > + case INDEX_op_rotlv_vec: > + v2 = temp_tcgv_vec(arg_temp(a2)); > + t1 = tcg_temp_new_vec(type); > + tcg_gen_neg_vec(vece, t1, v2); > + vec_gen_3(INDEX_op_shrv_vec, type, vece, tcgv_vec_arg(t1), > + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); > + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0), > + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); > + tcg_gen_or_vec(vece, v0, v0, t1); > + tcg_temp_free_vec(t1); > + break; > + case INDEX_op_rotrv_vec: > + v2 = temp_tcgv_vec(arg_temp(a2)); > + t1 = tcg_temp_new_vec(type); > + tcg_gen_neg_vec(vece, t1, v2); > + vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1), > + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); > + vec_gen_3(INDEX_op_shrv_vec, type, vece, tcgv_vec_arg(v0), > + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); > + tcg_gen_or_vec(vece, v0, v0, t1); > + tcg_temp_free_vec(t1); > + break; And here we can use TCG_REG_V0 as the temporary, both for negation and shift intermediate. vrsub_vi V0, a2, 0 vshlv_vv V0, a1, V0 vshrv_vv a0, a1, a2 vor_vv a0, a0, V0 r~