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([2a01:e0a:466:71c0:703f:24ee:3c57:e184]) by smtp.gmail.com with ESMTPSA id v7sm5815129wrp.45.2020.06.17.01.16.57 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Jun 2020 01:16:58 -0700 (PDT) Mime-Version: 1.0 (Mac OS X Mail 13.4 \(3608.80.23.2.2\)) Subject: Re: ovmf / PCI passthrough impaired due to very limiting PCI64 aperture From: Christophe de Dinechin In-Reply-To: <20200616165043.24y2cp53axk7uggy@sirius.home.kraxel.org> Date: Wed, 17 Jun 2020 10:16:55 +0200 Message-Id: <97D6912A-C840-4723-A32F-7B05FF827EB8@redhat.com> References: <99779e9c-f05f-501b-b4be-ff719f140a88@canonical.com> <20200616165043.24y2cp53axk7uggy@sirius.home.kraxel.org> To: Gerd Hoffmann X-Mailer: Apple Mail (2.3608.80.23.2.2) X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=207.211.31.81; envelope-from=cdupontd@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/17 01:42:42 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pedro.principeza@canonical.com, ehabkost@redhat.com, dann.frazier@canonical.com, "Guilherme G. Piccoli" , qemu-devel@nongnu.org, christian.ehrhardt@canonical.com, dgilbert@redhat.com, lersek@redhat.com, fw@gpiccoli.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" > Le 16 Jun 2020 =C3=A0 18:50, Gerd Hoffmann a =C3=A9cr= it : >=20 > Hi, >=20 >> (a) We could rely in the guest physbits to calculate the PCI64 aperture. >=20 > I'd love to do that. Move the 64-bit I/O window as high as possible and > use -- say -- 25% of the physical address space for it. >=20 > Problem is we can't. Is the only reason unreliable guest physbits? >=20 >> failure. Also, if the users are not setting the physbits in the guest, >> there must be a default (seems to be 40bit according to my experiments), >> seems to be a good idea to rely on that. >=20 > Yes, 40 is the default, and it is used *even if the host supports less > than that*. Typical values I've seen for intel hardware are 36 and 39. > 39 is used even by recent hardware (not the xeons, but check out a > laptop or a nuc). >=20 >> If guest physbits is 40, why to have OVMF limiting it to 36, right? >=20 > Things will explode in case OVMF uses more physbits than the host > supports (host physbits limit applies to ept too). In other words: OVMF > can't trust the guest physbits, so it is conservative to be on the safe > side. >=20 > If we can somehow make a *trustable* physbits value available to the > guest, then yes, we can go that route. But the guest physbits we have > today unfortunately don't cut it. What is the rationale for ever allowing guest physbits > host physbits? >=20 > take care, > Gerd >=20 >=20