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([2602:47:d48a:1201:b354:386:82db:58e7]) by smtp.gmail.com with ESMTPSA id e9-20020aa79809000000b0056c349f5c70sm651124pfl.79.2022.11.17.01.44.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Nov 2022 01:44:05 -0800 (PST) Message-ID: <97ceaca3-109e-ba04-30b2-c7f55c6ed422@linaro.org> Date: Thu, 17 Nov 2022 01:44:03 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v3 6/9] target/riscv: add support for Zcmp extension Content-Language: en-US To: Weiwei Li , palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com References: <20221117070316.58447-1-liweiwei@iscas.ac.cn> <20221117070316.58447-7-liweiwei@iscas.ac.cn> From: Richard Henderson In-Reply-To: <20221117070316.58447-7-liweiwei@iscas.ac.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/16/22 23:03, Weiwei Li wrote: > Add encode, trans* functions for Zcmp instructions > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > --- > target/riscv/insn16.decode | 18 ++ > target/riscv/insn_trans/trans_rvzce.c.inc | 242 +++++++++++++++++++++- > target/riscv/translate.c | 5 + > 3 files changed, 264 insertions(+), 1 deletion(-) Better, though... > +static bool gen_zcmp_check(DisasContext *ctx, arg_zcmp *a) > +{ > + /* rlist 0 to 3 are reserved for future EABI variant */ > + if (a->zcmp_rlist < 4) { > + return false; > + } > + > + /* rlist <= 6 when RV32E/RV64E */ > + if (ctx->cfg_ptr->ext_e && a->zcmp_rlist > 6) { > + return false; > + } > + > + return true; > +} This could be merged into... > + > +#define X_S0 8 > +#define X_S1 9 > +#define X_Sn 16 > + > +static inline void update_push_pop_list(target_ulong rlist, bool *xreg_list) ... here. For instance, one way is to return false when the list is invalid. Better is to return a uint32_t bitmap of the registers in the list, with 0 indicating invalid. Nit 1: Remove the inline. Nit 2: A better name might be decode_push_pop_list. > +static inline target_ulong caculate_stack_adj(int bytes, target_ulong rlist, > + target_ulong spimm) > +{ > + target_ulong stack_adj_base = 0; > + switch (rlist) { > + case 15: > + stack_adj_base = bytes == 4 ? 64 : 112; > + break; > + case 14: > + stack_adj_base = bytes == 4 ? 48 : 96; > + break; > + case 13: > + case 12: > + stack_adj_base = bytes == 4 ? 48 : 80; > + break; > + case 11: > + case 10: > + stack_adj_base = bytes == 4 ? 32 : 64; > + break; > + case 9: > + case 8: > + stack_adj_base = bytes == 4 ? 32 : 48; > + break; > + case 7: > + case 6: > + stack_adj_base = bytes == 4 ? 16 : 32; > + break; > + case 5: > + case 4: > + stack_adj_base = 16; > + break; > + } I really dislike this, as it replicates the decoding done just above. I think this ought to be simply: ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16) + spimm > +static bool gen_pop(DisasContext *ctx, arg_zcmp *a, bool ret, bool ret_val) > +{ > + REQUIRE_ZCMP(ctx); > + > + if (!gen_zcmp_check(ctx, a)) { > + return false; > + } > + > + bool xreg_list[32] = {false}; > + int bytes = get_ol(ctx) == MXL_RV32 ? 4 : 8; Better with MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TEUL : MO_TEUQ; int reg_size = memop_size(memop); > + switch (bytes) { > + case 4: > + tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, MO_32); > + break; > + case 8: > + tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, MO_64); > + break; > + default: > + break; > + } These are incorrect in that they do not indicate the target endianness. Better to merge the two using the common memop computed above: tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop); > +static bool trans_cm_mvsa01(DisasContext *ctx, arg_cm_mvsa01 *a) > +{ > + REQUIRE_ZCMP(ctx); > + > + TCGv a0 = get_gpr(ctx, xA0, EXT_NONE); > + TCGv a1 = get_gpr(ctx, xA1, EXT_NONE); > + > + gen_set_gpr(ctx, a->rs1, a0); > + gen_set_gpr(ctx, a->rs2, a1); rs1 must not equal rs2. r~