From: David Hildenbrand <david@redhat.com>
To: Aurelien Jarno <aurelien@aurel32.net>,
Richard Henderson <rth@twiddle.net>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 2/5] target/s390x: Enforce instruction features
Date: Thu, 15 Jun 2017 13:28:51 +0200 [thread overview]
Message-ID: <97f3a8c2-5fc4-4df9-2372-f5b258ca7808@redhat.com> (raw)
In-Reply-To: <20170615070122.z44mdwhe25wlrn6q@aurel32.net>
On 15.06.2017 09:01, Aurelien Jarno wrote:
> On 2017-06-14 22:53, Richard Henderson wrote:
>> Signed-off-by: Richard Henderson <rth@twiddle.net>
>> ---
>> target/s390x/translate.c | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/target/s390x/translate.c b/target/s390x/translate.c
>> index af18ffb..48cee25 100644
>> --- a/target/s390x/translate.c
>> +++ b/target/s390x/translate.c
>> @@ -55,6 +55,7 @@ typedef struct DisasFields DisasFields;
>>
>> struct DisasContext {
>> struct TranslationBlock *tb;
>> + const unsigned long *features;
>> const DisasInsn *insn;
>> DisasFields *fields;
>> uint64_t ex_value;
>> @@ -5600,6 +5601,12 @@ static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
>> }
>> #endif
>>
>> + /* Check for insn feature enabled. */
>> + if (!test_bit(insn->fac, s->features)) {
>> + gen_program_exception(s, PGM_OPERATION);
>> + return EXIT_NORETURN;
>> + }
>> +
>> /* Check for insn specification exceptions. */
>> if (insn->spec) {
>> int spec = insn->spec, excp = 0, r;
>> @@ -5726,6 +5733,7 @@ void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb)
>> }
>>
>> dc.tb = tb;
>> + dc.features = cpu->model->features;
>> dc.pc = pc_start;
>> dc.cc_op = CC_OP_DYNAMIC;
>> dc.ex_value = tb->cs_base;
>
> It looks correct technically. Now I am not sure we want to do that,
> without at least provided a user to enable those instructions. There are
> a lot facilities that are partially implemented, usually because only
> the really used instructions are implemented, but also because some
> facilities are grouped in a single feature bit. This includes for
> example FPE, LPP, MIE, LAT, IEEEE_SIM and more.
A "sane" guest (e.g. Linux) will only use an instruction if the
corresponding stfl(e) bit is set. So in my opinion, this should be just
fine. If the bit is not set currently, the guest will not use it == dead
code.
>
> We could maybe provide a way to override the check, or only enable
> enforcement for fully implemented facilities. Failing to do so means we
> just introduce a regression from the user point of view (many binaries
> will stop working) and also that we change thousand of lines of code
> into dead code.
We should look continue implementing missing instructions to "unlock"
these features, so we can finally enable them in the CPU model, and
therefore indicate them to the guest.
>
> Aurelien
>
--
Thanks,
David
next prev parent reply other threads:[~2017-06-15 11:29 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-15 5:53 [Qemu-devel] [PATCH 0/5] More s390x improvements Richard Henderson
2017-06-15 5:53 ` [Qemu-devel] [PATCH 1/5] target/s390x: Map existing FAC_* names to S390_FEAT_* names Richard Henderson
2017-06-15 5:53 ` [Qemu-devel] [PATCH 2/5] target/s390x: Enforce instruction features Richard Henderson
2017-06-15 7:01 ` Aurelien Jarno
2017-06-15 11:28 ` David Hildenbrand [this message]
2017-06-15 12:53 ` Aurelien Jarno
2017-06-15 13:10 ` David Hildenbrand
2017-06-15 20:55 ` Aurelien Jarno
2017-06-15 5:53 ` [Qemu-devel] [PATCH 3/5] target/s390x: change PSW_SHIFT_KEY Richard Henderson
2017-06-15 5:53 ` [Qemu-devel] [PATCH 4/5] target/s390x: implement mvcos instruction Richard Henderson
2017-06-15 5:53 ` [Qemu-devel] [PATCH 5/5] target/s390x: mark CSST, CSST2, FPSEH facilities as available Richard Henderson
2017-06-15 9:02 ` Thomas Huth
2017-06-15 15:55 ` Richard Henderson
2017-06-15 20:49 ` Aurelien Jarno
2017-06-15 21:10 ` Richard Henderson
2017-06-15 21:19 ` Aurelien Jarno
2017-06-15 7:51 ` [Qemu-devel] [PATCH 0/5] More s390x improvements no-reply
2017-06-15 7:59 ` no-reply
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