* [RFC PATCH 1/3] include/hw/arm: move BSA definitions to bsa.h
2023-09-14 12:01 [RFC PATCH 0/3] Refactor PPI logic/definitions for virt/sbsa-ref Leif Lindholm
@ 2023-09-14 12:01 ` Leif Lindholm
2023-09-14 12:01 ` [RFC PATCH 2/3] {include/}hw/arm: refactor BSA/virt PPI logic Leif Lindholm
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: Leif Lindholm @ 2023-09-14 12:01 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Radoslaw Biernacki, Peter Maydell, Marcin Juszkiewicz
virt.h defines a number of IRQs that are ultimately described by Arm's
Base System Architecture specification. Move these to a dedicated header
so that they can be reused by other platforms that do the same.
Include that header from virt.h to minimise churn.
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
---
include/hw/arm/bsa.h | 35 +++++++++++++++++++++++++++++++++++
include/hw/arm/virt.h | 12 +-----------
2 files changed, 36 insertions(+), 11 deletions(-)
create mode 100644 include/hw/arm/bsa.h
diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h
new file mode 100644
index 0000000000..8277b3a379
--- /dev/null
+++ b/include/hw/arm/bsa.h
@@ -0,0 +1,35 @@
+/*
+ * Common definitions for Arm Base System Architecture (BSA) platforms.
+ *
+ * Copyright (c) 2015 Linaro Limited
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef QEMU_ARM_BSA_H
+#define QEMU_ARM_BSA_H
+
+#define ARCH_GIC_MAINT_IRQ 9
+
+#define ARCH_TIMER_VIRT_IRQ 11
+#define ARCH_TIMER_S_EL1_IRQ 13
+#define ARCH_TIMER_NS_EL1_IRQ 14
+#define ARCH_TIMER_NS_EL2_IRQ 10
+
+#define VIRTUAL_PMU_IRQ 7
+
+#define PPI(irq) ((irq) + 16)
+
+#endif /* QEMU_ARM_BSA_H */
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index e1ddbea96b..f69239850e 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -34,6 +34,7 @@
#include "qemu/notify.h"
#include "hw/boards.h"
#include "hw/arm/boot.h"
+#include "hw/arm/bsa.h"
#include "hw/block/flash.h"
#include "sysemu/kvm.h"
#include "hw/intc/arm_gicv3_common.h"
@@ -43,17 +44,6 @@
#define NUM_VIRTIO_TRANSPORTS 32
#define NUM_SMMU_IRQS 4
-#define ARCH_GIC_MAINT_IRQ 9
-
-#define ARCH_TIMER_VIRT_IRQ 11
-#define ARCH_TIMER_S_EL1_IRQ 13
-#define ARCH_TIMER_NS_EL1_IRQ 14
-#define ARCH_TIMER_NS_EL2_IRQ 10
-
-#define VIRTUAL_PMU_IRQ 7
-
-#define PPI(irq) ((irq) + 16)
-
/* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
#define PVTIME_SIZE_PER_CPU 64
--
2.30.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* [RFC PATCH 2/3] {include/}hw/arm: refactor BSA/virt PPI logic
2023-09-14 12:01 [RFC PATCH 0/3] Refactor PPI logic/definitions for virt/sbsa-ref Leif Lindholm
2023-09-14 12:01 ` [RFC PATCH 1/3] include/hw/arm: move BSA definitions to bsa.h Leif Lindholm
@ 2023-09-14 12:01 ` Leif Lindholm
2023-09-14 12:26 ` Philippe Mathieu-Daudé
2023-09-14 12:01 ` [RFC PATCH 3/3] hw/arm/sbsa-ref: use bsa.h for PPI definitions Leif Lindholm
2023-09-14 13:15 ` [RFC PATCH 0/3] Refactor PPI logic/definitions for virt/sbsa-ref Marcin Juszkiewicz
3 siblings, 1 reply; 8+ messages in thread
From: Leif Lindholm @ 2023-09-14 12:01 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Radoslaw Biernacki, Peter Maydell, Marcin Juszkiewicz
GIC Private Peripheral Interrupts (PPI) are defined as GIC INTID 16-31.
As in, PPI0 is INTID16 .. PPI15 is INTID31.
Arm's Base System Architecture specification (BSA) lists the mandated and
recommended private interrupt IDs by INTID, not by PPI index. But current
definitions in qemu define them by PPI index, complicating cross
referencing.
Meanwhile, the PPI(x) macro counterintuitively adds 16 to the input value,
converting a PPI index to an INTID.
Resolve this by redefining the BSA-allocated PPIs by their INTIDs,
inverting the logic of the PPI(x) macro and flipping where it is used.
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
---
hw/arm/virt-acpi-build.c | 4 ++--
hw/arm/virt.c | 9 +++++----
include/hw/arm/bsa.h | 14 +++++++-------
3 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 6b674231c2..963c58a88a 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -729,9 +729,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
uint64_t physical_base_address = 0, gich = 0, gicv = 0;
- uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0;
+ uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0;
uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
- PPI(VIRTUAL_PMU_IRQ) : 0;
+ VIRTUAL_PMU_IRQ : 0;
if (vms->gic_version == VIRT_GIC_VERSION_2) {
physical_base_address = memmap[VIRT_GIC_CPU].base;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 8ad78b23c2..bb70f3eec8 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -815,23 +815,24 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
qdev_connect_gpio_out(cpudev, irq,
qdev_get_gpio_in(vms->gic,
- ppibase + timer_irq[irq]));
+ ppibase
+ + PPI(timer_irq[irq])));
}
if (vms->gic_version != VIRT_GIC_VERSION_2) {
qemu_irq irq = qdev_get_gpio_in(vms->gic,
- ppibase + ARCH_GIC_MAINT_IRQ);
+ ppibase + PPI(ARCH_GIC_MAINT_IRQ));
qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
0, irq);
} else if (vms->virt) {
qemu_irq irq = qdev_get_gpio_in(vms->gic,
- ppibase + ARCH_GIC_MAINT_IRQ);
+ ppibase + PPI(ARCH_GIC_MAINT_IRQ));
sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
}
qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
qdev_get_gpio_in(vms->gic, ppibase
- + VIRTUAL_PMU_IRQ));
+ + PPI(VIRTUAL_PMU_IRQ)));
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
sysbus_connect_irq(gicbusdev, i + smp_cpus,
diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h
index 8277b3a379..b7db1cacf1 100644
--- a/include/hw/arm/bsa.h
+++ b/include/hw/arm/bsa.h
@@ -21,15 +21,15 @@
#ifndef QEMU_ARM_BSA_H
#define QEMU_ARM_BSA_H
-#define ARCH_GIC_MAINT_IRQ 9
+#define ARCH_GIC_MAINT_IRQ 25
-#define ARCH_TIMER_VIRT_IRQ 11
-#define ARCH_TIMER_S_EL1_IRQ 13
-#define ARCH_TIMER_NS_EL1_IRQ 14
-#define ARCH_TIMER_NS_EL2_IRQ 10
+#define ARCH_TIMER_VIRT_IRQ 27
+#define ARCH_TIMER_S_EL1_IRQ 29
+#define ARCH_TIMER_NS_EL1_IRQ 30
+#define ARCH_TIMER_NS_EL2_IRQ 26
-#define VIRTUAL_PMU_IRQ 7
+#define VIRTUAL_PMU_IRQ 23
-#define PPI(irq) ((irq) + 16)
+#define PPI(irq) ((irq) - 16)
#endif /* QEMU_ARM_BSA_H */
--
2.30.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [RFC PATCH 2/3] {include/}hw/arm: refactor BSA/virt PPI logic
2023-09-14 12:01 ` [RFC PATCH 2/3] {include/}hw/arm: refactor BSA/virt PPI logic Leif Lindholm
@ 2023-09-14 12:26 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 8+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-09-14 12:26 UTC (permalink / raw)
To: Leif Lindholm, qemu-devel
Cc: qemu-arm, Radoslaw Biernacki, Peter Maydell, Marcin Juszkiewicz
On 14/9/23 14:01, Leif Lindholm wrote:
> GIC Private Peripheral Interrupts (PPI) are defined as GIC INTID 16-31.
> As in, PPI0 is INTID16 .. PPI15 is INTID31.
> Arm's Base System Architecture specification (BSA) lists the mandated and
> recommended private interrupt IDs by INTID, not by PPI index. But current
> definitions in qemu define them by PPI index, complicating cross
> referencing.
>
> Meanwhile, the PPI(x) macro counterintuitively adds 16 to the input value,
> converting a PPI index to an INTID.
>
> Resolve this by redefining the BSA-allocated PPIs by their INTIDs,
> inverting the logic of the PPI(x) macro and flipping where it is used.
>
> Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
> ---
> hw/arm/virt-acpi-build.c | 4 ++--
> hw/arm/virt.c | 9 +++++----
> include/hw/arm/bsa.h | 14 +++++++-------
> 3 files changed, 14 insertions(+), 13 deletions(-)
Isn't it simpler to reorder patches 1 <-> 2?
(First fix PPI macro use within virt.c, then expose header)
^ permalink raw reply [flat|nested] 8+ messages in thread
* [RFC PATCH 3/3] hw/arm/sbsa-ref: use bsa.h for PPI definitions
2023-09-14 12:01 [RFC PATCH 0/3] Refactor PPI logic/definitions for virt/sbsa-ref Leif Lindholm
2023-09-14 12:01 ` [RFC PATCH 1/3] include/hw/arm: move BSA definitions to bsa.h Leif Lindholm
2023-09-14 12:01 ` [RFC PATCH 2/3] {include/}hw/arm: refactor BSA/virt PPI logic Leif Lindholm
@ 2023-09-14 12:01 ` Leif Lindholm
2023-09-14 12:26 ` Philippe Mathieu-Daudé
2023-09-14 13:15 ` [RFC PATCH 0/3] Refactor PPI logic/definitions for virt/sbsa-ref Marcin Juszkiewicz
3 siblings, 1 reply; 8+ messages in thread
From: Leif Lindholm @ 2023-09-14 12:01 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Radoslaw Biernacki, Peter Maydell, Marcin Juszkiewicz
Use the private peripheral interrupt definitions from bsa.h instead of
defining them locally. Refactor to use PPI() to convert from INTID macro
where necessary.
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
---
hw/arm/sbsa-ref.c | 24 +++++++++++-------------
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index bc89eb4806..589b17e3bc 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -2,6 +2,7 @@
* ARM SBSA Reference Platform emulation
*
* Copyright (c) 2018 Linaro Limited
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Written by Hongbo Zhang <hongbo.zhang@linaro.org>
*
* This program is free software; you can redistribute it and/or modify it
@@ -30,6 +31,7 @@
#include "exec/hwaddr.h"
#include "kvm_arm.h"
#include "hw/arm/boot.h"
+#include "hw/arm/bsa.h"
#include "hw/arm/fdt.h"
#include "hw/arm/smmuv3.h"
#include "hw/block/flash.h"
@@ -55,13 +57,6 @@
#define NUM_SMMU_IRQS 4
#define NUM_SATA_PORTS 6
-#define VIRTUAL_PMU_IRQ 7
-#define ARCH_GIC_MAINT_IRQ 9
-#define ARCH_TIMER_VIRT_IRQ 11
-#define ARCH_TIMER_S_EL1_IRQ 13
-#define ARCH_TIMER_NS_EL1_IRQ 14
-#define ARCH_TIMER_NS_EL2_IRQ 10
-
enum {
SBSA_FLASH,
SBSA_MEM,
@@ -494,15 +489,18 @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
qdev_connect_gpio_out(cpudev, irq,
qdev_get_gpio_in(sms->gic,
- ppibase + timer_irq[irq]));
+ ppibase
+ + PPI(timer_irq[irq])));
}
+ irq = qdev_get_gpio_in(sms->gic,
+ ppibase + PPI(ARCH_GIC_MAINT_IRQ));
qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
- qdev_get_gpio_in(sms->gic, ppibase
- + ARCH_GIC_MAINT_IRQ));
- qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
- qdev_get_gpio_in(sms->gic, ppibase
- + VIRTUAL_PMU_IRQ));
+ irq);
+
+ irq = qdev_get_gpio_in(sms->gic,
+ ppibase + PPI(VIRTUAL_PMU_IRQ));
+ qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, irq);
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
sysbus_connect_irq(gicbusdev, i + smp_cpus,
--
2.30.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [RFC PATCH 0/3] Refactor PPI logic/definitions for virt/sbsa-ref
2023-09-14 12:01 [RFC PATCH 0/3] Refactor PPI logic/definitions for virt/sbsa-ref Leif Lindholm
` (2 preceding siblings ...)
2023-09-14 12:01 ` [RFC PATCH 3/3] hw/arm/sbsa-ref: use bsa.h for PPI definitions Leif Lindholm
@ 2023-09-14 13:15 ` Marcin Juszkiewicz
2023-09-14 15:06 ` Leif Lindholm
3 siblings, 1 reply; 8+ messages in thread
From: Marcin Juszkiewicz @ 2023-09-14 13:15 UTC (permalink / raw)
To: Leif Lindholm, qemu-devel; +Cc: qemu-arm, Radoslaw Biernacki, Peter Maydell
W dniu 14.09.2023 o 14:01, Leif Lindholm pisze:
> While reviewing Marcin's patch this morning, cross referencing different
> specifications and looking at various places around the source code in
> order to convinced myself he really hadn't missed something out (the
> existing plumbing made it *so* clean to add), my brain broke slightly
> at keeping track of PPIs/INTIDs between the various sources.
>
> Moreover, I found the PPI() macro in virt.h to be doing the exact
> opposite of what I would have expected it to (it converts a PPI to an
> INTID rather than the other way around).
>
> So I refactored stuff so that:
> - PPIs defined by BSA are moved to a (new) common header.
> - The _IRQ definitions for those PPIs refer to the INTIDs.
> - sbsa-ref and virt both use these definitions.
>
> This change does objectively add a bit more noise to the code, since it
> means more locations need to use the PPI macro than before, but it felt
> like a readability improvement to me.
I like how code looks after those changes. No more adding 16 to irq
numbers to fit them into BSA spec numbers is nice to have.
Will rebase my "non-secure EL2 virtual timer" patch on top of it.
> Not even compilation tested, just the least confusing way of asking
> whether the change could be accepted at all.
There are build warnings and final binary segfaults on start.
--------------------------------------------
[1799/2931] Compiling C object libqemu-aarch64-softmmu.fa.p/hw_arm_sbsa-ref.c.o
../hw/arm/sbsa-ref.c: In function ‘create_gic’:
../hw/arm/sbsa-ref.c:496:13: warning: assignment to ‘int’ from ‘qemu_irq’ {aka ‘struct IRQState *’} makes integer from pointer without a cast [-Wint-conversion]
496 | irq = qdev_get_gpio_in(sms->gic,
| ^
../hw/arm/sbsa-ref.c:499:37: warning: passing argument 4 of ‘qdev_connect_gpio_out_named’ makes pointer from integer without a cast [-Wint-conversion]
499 | irq);
| ^~~
| |
| int
In file included from /home/marcin/devel/linaro/sbsa-qemu/code/qemu/include/hw/core/cpu.h:23,
from ../target/arm/cpu-qom.h:23,
from ../target/arm/cpu.h:26,
from /home/marcin/devel/linaro/sbsa-qemu/code/qemu/include/sysemu/kvm.h:244,
from ../hw/arm/sbsa-ref.c:27:
/home/marcin/devel/linaro/sbsa-qemu/code/qemu/include/hw/qdev-core.h:699:43: note: expected ‘qemu_irq’ {aka ‘struct IRQState *’} but argument is of type ‘int’
699 | qemu_irq input_pin);
| ~~~~~~~~~^~~~~~~~~
../hw/arm/sbsa-ref.c:501:13: warning: assignment to ‘int’ from ‘qemu_irq’ {aka ‘struct IRQState *’} makes integer from pointer without a cast [-Wint-conversion]
501 | irq = qdev_get_gpio_in(sms->gic,
| ^
../hw/arm/sbsa-ref.c:503:65: warning: passing argument 4 of ‘qdev_connect_gpio_out_named’ makes pointer from integer without a cast [-Wint-conversion]
503 | qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, irq);
| ^~~
| |
| int
/home/marcin/devel/linaro/sbsa-qemu/code/qemu/include/hw/qdev-core.h:699:43: note: expected ‘qemu_irq’ {aka ‘struct IRQState *’} but argument is of type ‘int’
699 | qemu_irq input_pin);
| ~~~~~~~~~^~~~~~~~~
--------------------------------------------
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [RFC PATCH 0/3] Refactor PPI logic/definitions for virt/sbsa-ref
2023-09-14 13:15 ` [RFC PATCH 0/3] Refactor PPI logic/definitions for virt/sbsa-ref Marcin Juszkiewicz
@ 2023-09-14 15:06 ` Leif Lindholm
0 siblings, 0 replies; 8+ messages in thread
From: Leif Lindholm @ 2023-09-14 15:06 UTC (permalink / raw)
To: Marcin Juszkiewicz, qemu-devel
Cc: qemu-arm, Radoslaw Biernacki, Peter Maydell
On 2023-09-14 14:15, Marcin Juszkiewicz wrote:
> W dniu 14.09.2023 o 14:01, Leif Lindholm pisze:
>> While reviewing Marcin's patch this morning, cross referencing different
>> specifications and looking at various places around the source code in
>> order to convinced myself he really hadn't missed something out (the
>> existing plumbing made it *so* clean to add), my brain broke slightly
>> at keeping track of PPIs/INTIDs between the various sources.
>>
>> Moreover, I found the PPI() macro in virt.h to be doing the exact
>> opposite of what I would have expected it to (it converts a PPI to an
>> INTID rather than the other way around).
>>
>> So I refactored stuff so that:
>> - PPIs defined by BSA are moved to a (new) common header.
>> - The _IRQ definitions for those PPIs refer to the INTIDs.
>> - sbsa-ref and virt both use these definitions.
>>
>> This change does objectively add a bit more noise to the code, since it
>> means more locations need to use the PPI macro than before, but it felt
>> like a readability improvement to me.
>
> I like how code looks after those changes. No more adding 16 to irq
> numbers to fit them into BSA spec numbers is nice to have.
>
> Will rebase my "non-secure EL2 virtual timer" patch on top of it.
>
>> Not even compilation tested, just the least confusing way of asking
>> whether the change could be accepted at all.
>
> There are build warnings and final binary segfaults on start.
Ah, yes. In my rush, I failed to spot that the -virt gic_create function
contained shadows of different type variables called irq.
Will address if there's a v1.
Thanks!
/
Leif
> --------------------------------------------
> [1799/2931] Compiling C object
> libqemu-aarch64-softmmu.fa.p/hw_arm_sbsa-ref.c.o
> ../hw/arm/sbsa-ref.c: In function ‘create_gic’:
> ../hw/arm/sbsa-ref.c:496:13: warning: assignment to ‘int’ from
> ‘qemu_irq’ {aka ‘struct IRQState *’} makes integer from pointer without
> a cast [-Wint-conversion]
> 496 | irq = qdev_get_gpio_in(sms->gic,
> | ^
> ../hw/arm/sbsa-ref.c:499:37: warning: passing argument 4 of
> ‘qdev_connect_gpio_out_named’ makes pointer from integer without a cast
> [-Wint-conversion]
> 499 | irq);
> | ^~~
> | |
> | int
> In file included from
> /home/marcin/devel/linaro/sbsa-qemu/code/qemu/include/hw/core/cpu.h:23,
> from ../target/arm/cpu-qom.h:23,
> from ../target/arm/cpu.h:26,
> from
> /home/marcin/devel/linaro/sbsa-qemu/code/qemu/include/sysemu/kvm.h:244,
> from ../hw/arm/sbsa-ref.c:27:
> /home/marcin/devel/linaro/sbsa-qemu/code/qemu/include/hw/qdev-core.h:699:43: note: expected ‘qemu_irq’ {aka ‘struct IRQState *’} but argument is of type ‘int’
> 699 | qemu_irq input_pin);
> | ~~~~~~~~~^~~~~~~~~
> ../hw/arm/sbsa-ref.c:501:13: warning: assignment to ‘int’ from
> ‘qemu_irq’ {aka ‘struct IRQState *’} makes integer from pointer without
> a cast [-Wint-conversion]
> 501 | irq = qdev_get_gpio_in(sms->gic,
> | ^
> ../hw/arm/sbsa-ref.c:503:65: warning: passing argument 4 of
> ‘qdev_connect_gpio_out_named’ makes pointer from integer without a cast
> [-Wint-conversion]
> 503 | qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
> irq);
> |
> ^~~
> | |
> |
> int
> /home/marcin/devel/linaro/sbsa-qemu/code/qemu/include/hw/qdev-core.h:699:43: note: expected ‘qemu_irq’ {aka ‘struct IRQState *’} but argument is of type ‘int’
> 699 | qemu_irq input_pin);
> | ~~~~~~~~~^~~~~~~~~
> --------------------------------------------
^ permalink raw reply [flat|nested] 8+ messages in thread