From: Richard Henderson <richard.henderson@linaro.org>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Cc: paul@nowt.org
Subject: Re: [PATCH v2 05/37] target/i386: add core of new i386 decoder
Date: Sat, 24 Sep 2022 15:09:21 +0000 [thread overview]
Message-ID: <9875ffeb-ad97-e6b5-cc52-942f7211dd95@linaro.org> (raw)
In-Reply-To: <20220920172507.95568-6-pbonzini@redhat.com>
On 9/20/22 17:24, Paolo Bonzini wrote:
> The new decoder is based on three principles:
>
> - use mostly table-driven decoding, using tables derived as much as possible
> from the Intel manual. Centralizing the decode the operands makes it
> more homogeneous, for example all immediates are signed. All modrm
> handling is in one function, and can be shared between SSE and ALU
> instructions (including XMM<->GPR instructions). The SSE/AVX decoder
> will also not have duplicated code between the 0F, 0F38 and 0F3A tables.
>
> - keep the code as "non-branchy" as possible. Generally, the code for
> the new decoder is more verbose, but the control flow is simpler.
> Conditionals are not nested and have small bodies. All instruction
> groups are resolved even before operands are decoded, and code
> generation is separated as much as possible within small functions
> that only handle one instruction each.
>
> - keep address generation and (for ALU operands) memory loads and writeback
> as much in common code as possible. All ALU operations for example
> are implemented as T0=f(T0,T1). For non-ALU instructions,
> read-modify-write memory operations are rare, but registers do not
> have TCGv equivalents: therefore, the common logic sets up pointer
> temporaries with the operands, while load and writeback are handled
> by gvec or by helpers.
>
> These principles make future code review and extensibility simpler, at
> the cost of having a relatively large amount of code in the form of this
> patch. Even EVEX should not be_too_ hard to implement (it's just a crazy
> large amount of possibilities).
>
> This patch introduces the main decoder flow, and integrates the old
> decoder with the new one. The old decoder takes care of parsing
> prefixes and then optionally drops to the new one. The changes to the
> old decoder are minimal and allow it to be replaced incrementally with
> the new one.
>
> There is a debugging mechanism through a "LIMIT" environment variable.
> In user-mode emulation, the variable is the number of instructions
> decoded by the new decoder before permanently switching to the old one.
> In system emulation, the variable is the highest opcode that is decoded
> by the new decoder (this is less friendly, but it's the best that can
> be done without requiring deterministic execution).
>
> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> ---
> target/i386/tcg/decode-new.c.inc | 748 +++++++++++++++++++++++++++++++
> target/i386/tcg/decode-new.h | 181 ++++++++
> target/i386/tcg/emit.c.inc | 31 ++
> target/i386/tcg/translate.c | 68 ++-
> 4 files changed, 1020 insertions(+), 8 deletions(-)
> create mode 100644 target/i386/tcg/decode-new.c.inc
> create mode 100644 target/i386/tcg/decode-new.h
> create mode 100644 target/i386/tcg/emit.c.inc
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2022-09-24 15:10 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-20 17:24 [PATCH v2 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
2022-09-20 17:24 ` [PATCH v2 01/37] target/i386: Define XMMReg and access macros, align ZMM registers Paolo Bonzini
2022-09-20 17:24 ` [PATCH v2 02/37] target/i386: make ldo/sto operations consistent with ldq Paolo Bonzini
2022-09-24 15:00 ` Richard Henderson
2022-09-20 17:24 ` [PATCH v2 03/37] target/i386: REPZ and REPNZ are mutually exclusive Paolo Bonzini
2022-09-20 17:24 ` [PATCH v2 04/37] target/i386: introduce insn_get_addr Paolo Bonzini
2022-09-20 17:24 ` [PATCH v2 05/37] target/i386: add core of new i386 decoder Paolo Bonzini
2022-09-24 15:09 ` Richard Henderson [this message]
2022-09-20 17:24 ` [PATCH v2 06/37] target/i386: add ALU load/writeback core Paolo Bonzini
2022-09-24 15:13 ` Richard Henderson
2022-09-20 17:24 ` [PATCH v2 07/37] target/i386: add CPUID[EAX=7, ECX=0].ECX to DisasContext Paolo Bonzini
2022-09-20 17:24 ` [PATCH v2 08/37] target/i386: add CPUID feature checks to new decoder Paolo Bonzini
2022-09-20 17:24 ` [PATCH v2 09/37] target/i386: add AVX_EN hflag Paolo Bonzini
2022-09-20 17:24 ` [PATCH v2 10/37] target/i386: validate VEX prefixes via the instructions' exception classes Paolo Bonzini
2022-09-24 20:19 ` Richard Henderson
2022-09-20 17:24 ` [PATCH v2 11/37] target/i386: validate SSE prefixes directly in the decoding table Paolo Bonzini
2022-09-24 20:23 ` Richard Henderson
2022-09-20 17:24 ` [PATCH v2 12/37] target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder Paolo Bonzini
2022-09-20 17:24 ` [PATCH v2 13/37] target/i386: Prepare ops_sse_header.h for 256 bit AVX Paolo Bonzini
2022-09-20 17:24 ` [PATCH v2 14/37] target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Paolo Bonzini
2022-09-20 17:24 ` [PATCH v2 15/37] target/i386: support operand merging in binary scalar helpers Paolo Bonzini
2022-09-20 17:24 ` [PATCH v2 16/37] target/i386: provide 3-operand versions of unary " Paolo Bonzini
2022-09-20 17:24 ` [PATCH v2 17/37] target/i386: implement additional AVX comparison operators Paolo Bonzini
2022-09-20 17:24 ` [PATCH v2 18/37] target/i386: Introduce 256-bit vector helpers Paolo Bonzini
2022-09-20 17:24 ` [PATCH v2 19/37] target/i386: reimplement 0x0f 0x60-0x6f, add AVX Paolo Bonzini
2022-09-24 20:31 ` Richard Henderson
2022-09-20 17:24 ` [PATCH v2 20/37] target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, " Paolo Bonzini
2022-09-24 20:32 ` Richard Henderson
2022-09-20 17:24 ` [PATCH v2 21/37] target/i386: reimplement 0x0f 0x50-0x5f, " Paolo Bonzini
2022-09-24 20:37 ` Richard Henderson
2022-09-20 17:24 ` [PATCH v2 22/37] target/i386: reimplement 0x0f 0x78-0x7f, " Paolo Bonzini
2022-09-24 20:43 ` Richard Henderson
2022-09-26 7:24 ` Paolo Bonzini
2022-09-26 7:46 ` Richard Henderson
2022-09-20 17:24 ` [PATCH v2 23/37] target/i386: reimplement 0x0f 0x70-0x77, " Paolo Bonzini
2022-09-24 20:53 ` Richard Henderson
2022-09-20 17:24 ` [PATCH v2 24/37] target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, " Paolo Bonzini
2022-09-24 20:56 ` Richard Henderson
2022-09-26 7:56 ` Paolo Bonzini
2022-09-20 17:24 ` [PATCH v2 25/37] target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes Paolo Bonzini
2022-09-24 20:57 ` Richard Henderson
2022-09-20 17:24 ` [PATCH v2 26/37] target/i386: reimplement 0x0f 0x3a, add AVX Paolo Bonzini
2022-09-24 21:02 ` Richard Henderson
2022-09-20 17:24 ` [PATCH v2 27/37] target/i386: Use tcg gvec ops for pmovmskb Paolo Bonzini
2022-09-24 21:08 ` Richard Henderson
2022-09-20 17:24 ` [PATCH v2 28/37] target/i386: reimplement 0x0f 0x38, add AVX Paolo Bonzini
2022-09-24 21:14 ` Richard Henderson
2022-09-20 17:24 ` [PATCH v2 29/37] target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, " Paolo Bonzini
2022-09-20 17:25 ` [PATCH v2 30/37] target/i386: reimplement 0x0f 0x10-0x17, " Paolo Bonzini
2022-09-24 21:16 ` Richard Henderson
2022-09-20 17:25 ` [PATCH v2 31/37] target/i386: reimplement 0x0f 0x28-0x2f, " Paolo Bonzini
2022-09-24 21:18 ` Richard Henderson
2022-09-20 17:25 ` [PATCH v2 32/37] target/i386: implement XSAVE and XRSTOR of AVX registers Paolo Bonzini
2022-09-24 21:19 ` Richard Henderson
2022-09-20 17:25 ` [PATCH v2 33/37] target/i386: implement VLDMXCSR/VSTMXCSR Paolo Bonzini
2022-09-24 21:20 ` Richard Henderson
2022-09-20 17:25 ` [PATCH v2 34/37] target/i386: Enable AVX cpuid bits when using TCG Paolo Bonzini
2022-09-20 17:25 ` [PATCH v2 35/37] tests/tcg: extend SSE tests to AVX Paolo Bonzini
2022-09-20 17:25 ` [PATCH v2 36/37] target/i386: move 3DNow to the new decoder Paolo Bonzini
2022-09-24 21:24 ` Richard Henderson
2022-09-20 17:25 ` [PATCH v2 37/37] target/i386: remove old SSE decoder Paolo Bonzini
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