From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v2 14/23] target/arm: Convert load/store-pair to decodetree
Date: Wed, 14 Jun 2023 07:30:34 +0200 [thread overview]
Message-ID: <98a4691a-db64-76e4-449f-4b4983cf166e@linaro.org> (raw)
In-Reply-To: <20230611160032.274823-15-peter.maydell@linaro.org>
On 6/11/23 18:00, Peter Maydell wrote:
> Convert the load/store register pair insns (LDP, STP,
> LDNP, STNP, LDPSW, STGP) to decodetree.
>
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> Message-id:20230602155223.2040685-12-peter.maydell@linaro.org
> ---
> This was reviewed in v1, but the underlying code
> changed enough in the atomic-ops work that I've dropped
> the R-by tag.
> ---
> target/arm/tcg/a64.decode | 61 +++++
> target/arm/tcg/translate-a64.c | 425 ++++++++++++++++-----------------
> 2 files changed, 271 insertions(+), 215 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> +static bool trans_STP(DisasContext *s, arg_ldstpair *a)
> +{
> + uint64_t offset = a->imm << a->sz;
> + TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2;
> + MemOp mop = finalize_memop(s, a->sz);
> +
> + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, true, mop);
> + tcg_rt = cpu_reg(s, a->rt);
> + tcg_rt2 = cpu_reg(s, a->rt2);
> + /*
> + * We built mop above for the single logical access -- rebuild it
> + * now for the paired operation.
> + *
> + * With LSE2, non-sign-extending pairs are treated atomically if
> + * aligned, and if unaligned one of the pair will be completely
> + * within a 16-byte block and that element will be atomic.
> + * Otherwise each element is separately atomic.
> + * In all cases, issue one operation with the correct atomicity.
> + *
> + * This treats sign-extending loads like zero-extending loads,
> + * since that reuses the most code below.
> + */
Could lose the bit about loads within the store function.
r~
next prev parent reply other threads:[~2023-06-14 5:31 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-11 16:00 [PATCH v2 00/23] target/arm: Convert exception, system, loads and stores to decodetree Peter Maydell
2023-06-11 16:00 ` [PATCH v2 01/23] target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics Peter Maydell
2023-06-11 16:00 ` [PATCH v2 02/23] target/arm: Return correct result for LDG when ATA=0 Peter Maydell
2023-06-11 16:00 ` [PATCH v2 03/23] target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode Peter Maydell
2023-06-12 9:31 ` Philippe Mathieu-Daudé
2023-06-14 5:18 ` Richard Henderson
2023-06-11 16:00 ` [PATCH v2 04/23] target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores Peter Maydell
2023-06-14 5:20 ` Richard Henderson
2023-06-11 16:00 ` [PATCH v2 05/23] target/arm: Convert hint instruction space to decodetree Peter Maydell
2023-06-11 16:00 ` [PATCH v2 06/23] target/arm: Convert barrier insns " Peter Maydell
2023-06-12 9:37 ` Philippe Mathieu-Daudé
2023-06-11 16:00 ` [PATCH v2 07/23] target/arm: Convert CFINV, XAFLAG and AXFLAG " Peter Maydell
2023-06-11 16:00 ` [PATCH v2 08/23] target/arm: Convert MSR (immediate) " Peter Maydell
2023-06-11 16:00 ` [PATCH v2 09/23] target/arm: Convert MSR (reg), MRS, SYS, SYSL " Peter Maydell
2023-06-12 10:37 ` Philippe Mathieu-Daudé
2023-06-11 16:00 ` [PATCH v2 10/23] target/arm: Convert exception generation instructions " Peter Maydell
2023-06-11 16:00 ` [PATCH v2 11/23] target/arm: Convert load/store exclusive and ordered " Peter Maydell
2023-06-11 16:00 ` [PATCH v2 12/23] target/arm: Convert LDXP, STXP, CASP, CAS " Peter Maydell
2023-06-11 16:00 ` [PATCH v2 13/23] target/arm: Convert load reg (literal) group " Peter Maydell
2023-06-11 16:00 ` [PATCH v2 14/23] target/arm: Convert load/store-pair " Peter Maydell
2023-06-14 5:30 ` Richard Henderson [this message]
2023-06-11 16:00 ` [PATCH v2 15/23] target/arm: Convert ld/st reg+imm9 insns " Peter Maydell
2023-06-11 16:00 ` [PATCH v2 16/23] target/arm: Convert LDR/STR with 12-bit immediate " Peter Maydell
2023-06-11 16:00 ` [PATCH v2 17/23] target/arm: Convert LDR/STR reg+reg " Peter Maydell
2023-06-11 16:00 ` [PATCH v2 18/23] target/arm: Convert atomic memory ops " Peter Maydell
2023-06-11 16:00 ` [PATCH v2 19/23] target/arm: Convert load (pointer auth) insns " Peter Maydell
2023-06-11 16:00 ` [PATCH v2 20/23] target/arm: Convert LDAPR/STLR (imm) " Peter Maydell
2023-06-11 16:00 ` [PATCH v2 21/23] target/arm: Convert load/store (multiple structures) " Peter Maydell
2023-06-11 16:00 ` [PATCH v2 22/23] target/arm: Convert load/store single structure " Peter Maydell
2023-06-14 5:35 ` Richard Henderson
2023-06-11 16:00 ` [PATCH v2 23/23] target/arm: Convert load/store tags insns " Peter Maydell
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