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[90.182.62.66]) by smtp.gmail.com with ESMTPSA id o16-20020a1c7510000000b003f7e6d7f71esm16283945wmc.36.2023.06.13.22.30.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 Jun 2023 22:30:36 -0700 (PDT) Message-ID: <98a4691a-db64-76e4-449f-4b4983cf166e@linaro.org> Date: Wed, 14 Jun 2023 07:30:34 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v2 14/23] target/arm: Convert load/store-pair to decodetree Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20230611160032.274823-1-peter.maydell@linaro.org> <20230611160032.274823-15-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20230611160032.274823-15-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::12f; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x12f.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.098, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/11/23 18:00, Peter Maydell wrote: > Convert the load/store register pair insns (LDP, STP, > LDNP, STNP, LDPSW, STGP) to decodetree. > > Signed-off-by: Peter Maydell > Message-id:20230602155223.2040685-12-peter.maydell@linaro.org > --- > This was reviewed in v1, but the underlying code > changed enough in the atomic-ops work that I've dropped > the R-by tag. > --- > target/arm/tcg/a64.decode | 61 +++++ > target/arm/tcg/translate-a64.c | 425 ++++++++++++++++----------------- > 2 files changed, 271 insertions(+), 215 deletions(-) Reviewed-by: Richard Henderson > +static bool trans_STP(DisasContext *s, arg_ldstpair *a) > +{ > + uint64_t offset = a->imm << a->sz; > + TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2; > + MemOp mop = finalize_memop(s, a->sz); > + > + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, true, mop); > + tcg_rt = cpu_reg(s, a->rt); > + tcg_rt2 = cpu_reg(s, a->rt2); > + /* > + * We built mop above for the single logical access -- rebuild it > + * now for the paired operation. > + * > + * With LSE2, non-sign-extending pairs are treated atomically if > + * aligned, and if unaligned one of the pair will be completely > + * within a 16-byte block and that element will be atomic. > + * Otherwise each element is separately atomic. > + * In all cases, issue one operation with the correct atomicity. > + * > + * This treats sign-extending loads like zero-extending loads, > + * since that reuses the most code below. > + */ Could lose the bit about loads within the store function. r~