From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH 4/4] target/arm: Implement ARMv8.2-TTS2UXN
Date: Wed, 29 Apr 2020 11:43:18 -0700 [thread overview]
Message-ID: <98a9cb27-0a9c-b9c7-f683-968e01202343@linaro.org> (raw)
In-Reply-To: <20200330210400.11724-5-peter.maydell@linaro.org>
On 3/30/20 2:04 PM, Peter Maydell wrote:
> The ARMv8.2-TTS2UXN feature extends the XN field in stage 2
> translation table descriptors from just bit [54] to bits [54:53],
> allowing stage 2 to control execution permissions separately for EL0
> and EL1. Implement the new semantics of the XN field and enable
> the feature for our 'max' CPU.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/cpu.h | 15 +++++++++++++++
> target/arm/cpu.c | 1 +
> target/arm/cpu64.c | 2 ++
> target/arm/helper.c | 37 +++++++++++++++++++++++++++++++------
> 4 files changed, 49 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2020-04-29 18:46 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-30 21:03 [PATCH 0/4] arm: Implement ARMv8.2-TTS2UXN Peter Maydell
2020-03-30 21:03 ` [PATCH 1/4] target/arm: Don't use a TLB for ARMMMUIdx_Stage2 Peter Maydell
2020-04-29 18:39 ` Richard Henderson
2020-03-30 21:03 ` [PATCH 2/4] target/arm: Use enum constant in get_phys_addr_lpae() call Peter Maydell
2020-04-29 18:39 ` Richard Henderson
2020-03-30 21:03 ` [PATCH 3/4] target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae() Peter Maydell
2020-04-29 18:41 ` Richard Henderson
2020-03-30 21:04 ` [PATCH 4/4] target/arm: Implement ARMv8.2-TTS2UXN Peter Maydell
2020-04-29 18:43 ` Richard Henderson [this message]
2020-04-27 13:29 ` [PATCH 0/4] arm: " Peter Maydell
2020-04-27 16:04 ` Edgar E. Iglesias
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