From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41767) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bGJ2l-0006Cw-Rt for qemu-devel@nongnu.org; Fri, 24 Jun 2016 00:48:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bGJ2j-0007Rp-Qp for qemu-devel@nongnu.org; Fri, 24 Jun 2016 00:48:38 -0400 Sender: Richard Henderson References: <1466705806-679898-1-git-send-email-afarallax@yandex.ru> <2e0293e6-987c-43ec-e9c1-3a63aa593fb4@twiddle.net> From: Richard Henderson Message-ID: <98aa90b9-8f11-b613-1330-3ba79b8c5ac4@twiddle.net> Date: Thu, 23 Jun 2016 21:48:28 -0700 MIME-Version: 1.0 In-Reply-To: <2e0293e6-987c-43ec-e9c1-3a63aa593fb4@twiddle.net> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4] Improve the alignment check infrastructure List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sergey Sorokin , qemu-devel@nongnu.org Cc: Peter Crosthwaite , Claudio Fontana , Alexander Graf , qemu-arm@nongnu.org, Vassili Karpov , Paolo Bonzini On 06/23/2016 12:18 PM, Richard Henderson wrote: > On 06/23/2016 11:16 AM, Sergey Sorokin wrote: >> +#if defined(CONFIG_SOFTMMU) >> +/** >> + * get_alignment_bits >> + * @memop: TCGMemOp value >> + * >> + * Extract the alignment size from the memop. >> + * >> + * Returns: 0 in case of byte access (which is always aligned); >> + * positive value - number of alignment bits; >> + * negative value if unaligned access enabled >> + * and this is not a byte access. >> + */ >> +static inline int get_alignment_bits(TCGMemOp memop) >> +{ >> + int a = memop & MO_AMASK; >> + int s = memop & MO_SIZE; >> + >> + if (a == MO_UNALN) { >> + /* Negative value if unaligned access enabled, >> + * or zero value in case of byte access. >> + */ >> + return -s; >> + } else if (a == MO_ALIGN) { >> + tcg_debug_assert((TLB_FLAGS_MASK & ((1 << s) - 1)) == 0); >> + /* A natural alignment: return a number of access size bits */ >> + return s; >> + } else { >> + /* Specific alignment size. It must be equal or greater >> + * than the access size. >> + */ >> + a >>= MO_ASHIFT; >> + tcg_debug_assert(a >= s); >> + tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); >> + return a; >> + } >> +} >> +#endif /* CONFIG_SOFTMMU */ > > While it's true that usermode doesn't support alignment checks at all (either > direction, I'd prefer to leave the function available and isolate the one > assert that caused your build problem. E.g. > > static inline int get_alignment_bits(TCGMemOp memop) > { > int a = memop & MO_AMASK; > int s = memop & MO_SIZE; > int r; > > ... > } else if (a == MO_ALIGN) { > /* A natural alignment: return a number of access size bits */ > r = s; > } else { > /* Specific alignment size. It must be equal or greater > * than the access size. > */ > r = a >> MO_ASHIFT; > tcg_debug_assert(r >= s); > } > #ifdef CONFIG_SOFTMMU > /* Make sure requested alignment doesn't overlap TLB flags. */ > tcg_debug_assert((TLB_FLAGS_MASK & ((1 << r) - 1)) == 0); > #endif > return r; > } > > > I'll give this a test with some target-sparc changes where this will be useful. I've merged the patch with the above change for tcg-next. r~