From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: Re: [PULL 00/26] riscv-to-apply queue
Date: Fri, 3 Oct 2025 10:33:49 -0700 [thread overview]
Message-ID: <98b20903-1dd3-4ea1-a84e-921f2ce54e0d@linaro.org> (raw)
In-Reply-To: <20251003032718.1324734-1-alistair.francis@wdc.com>
On 10/2/25 20:26, alistair23@gmail.com wrote:
> From: Alistair Francis<alistair.francis@wdc.com>
>
> The following changes since commit 29b77c1a2db2d796bc3847852a5c8dc2a1e6e83b:
>
> Merge tag 'rust-ci-pull-request' ofhttps://gitlab.com/marcandre.lureau/qemu into staging (2025-09-30 09:29:38 -0700)
>
> are available in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20251003-3
>
> for you to fetch changes up to ad2a0aa2824b1dac9f61bac33980e866e9a88856:
>
> docs: riscv-iommu: Update status of kernel support (2025-10-03 13:17:04 +1000)
>
> ----------------------------------------------------------------
> First RISC-V PR for 10.2
>
> * Fix MSI table size limit
> * Add riscv64 to FirmwareArchitecture
> * Sync RISC-V hwprobe with Linux
> * Implement MonitorDef HMP API
> * Update OpenSBI to v1.7
> * Fix SiFive UART character drop issue and minor refactors
> * Fix RISC-V timer migration issues
> * Use riscv_cpu_is_32bit() when handling SBI_DBCN reg
> * Use riscv_csrr in riscv_csr_read
> * Align memory allocations to 2M on RISC-V
> * Do not use translator_ldl in opcode_at
> * Minor fixes of RISC-V CFI
> * Modify minimum VLEN rule
> * Fix vslide1[up|down].vx unexpected result when XLEN=32 and SEW=64
> * Fixup IOMMU PDT Nested Walk
> * Fix endianness swap on compressed instructions
> * Update status of IOMMU kernel support
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/10.2 as appropriate.
r~
next prev parent reply other threads:[~2025-10-03 17:37 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-03 3:26 [PULL 00/26] riscv-to-apply queue alistair23
2025-10-03 3:26 ` [PULL 01/26] hw/riscv/riscv-iommu: Fix MSI table size limit alistair23
2025-10-03 3:26 ` [PULL 02/26] docs/interop/firmware: Add riscv64 to FirmwareArchitecture alistair23
2025-10-03 3:26 ` [PULL 03/26] linux-user/syscall.c: sync RISC-V hwprobe with Linux alistair23
2025-10-03 3:26 ` [PULL 04/26] target/riscv: implement MonitorDef HMP API alistair23
2025-10-21 15:23 ` Peter Maydell
2025-10-21 18:06 ` Daniel Henrique Barboza
2025-10-03 3:26 ` [PULL 05/26] roms/opensbi: Update to v1.7 alistair23
2025-10-03 3:26 ` [PULL 06/26] hw/char: sifive_uart: Raise IRQ according to the Tx/Rx watermark thresholds alistair23
2025-10-03 3:26 ` [PULL 07/26] hw/char: sifive_uart: Avoid pushing Tx FIFO when size is zero alistair23
2025-10-03 3:27 ` [PULL 08/26] hw/char: sifive_uart: Remove outdated comment about Tx FIFO alistair23
2025-10-03 3:27 ` [PULL 09/26] hw/char: sifive_uart: Add newline to error message alistair23
2025-10-03 3:27 ` [PULL 10/26] hw/intc: Save time_delta in RISC-V mtimer VMState alistair23
2025-10-03 3:27 ` [PULL 11/26] migration: Add support for a variable-length array of UINT32 pointers alistair23
2025-10-03 3:27 ` [PULL 12/26] hw/intc: Save timers array in RISC-V mtimer VMState alistair23
2025-10-03 3:27 ` [PULL 13/26] target/riscv: Save stimer and vstimer in CPU vmstate alistair23
2025-10-03 3:27 ` [PULL 14/26] target/riscv/kvm: Use riscv_cpu_is_32bit() when handling SBI_DBCN reg alistair23
2025-10-03 3:27 ` [PULL 15/26] target/riscv: use riscv_csrr in riscv_csr_read alistair23
2025-10-03 3:27 ` [PULL 16/26] qemu/osdep: align memory allocations to 2M on RISC-V alistair23
2025-10-03 3:27 ` [PULL 17/26] target/riscv: do not use translator_ldl in opcode_at alistair23
2025-10-03 3:27 ` [PULL 18/26] target/riscv: Fix the mepc when sspopchk triggers the exception alistair23
2025-10-03 3:27 ` [PULL 19/26] target/riscv: Fix SSP CSR error handling in VU/VS mode alistair23
2025-10-03 3:27 ` [PULL 20/26] target/riscv: Fix ssamoswap error handling alistair23
2025-10-03 3:27 ` [PULL 21/26] target/riscv: rvv: Replace checking V by checking Zve32x alistair23
2025-10-03 3:27 ` [PULL 22/26] target/riscv: rvv: Modify minimum VLEN according to enabled vector extensions alistair23
2025-10-03 3:27 ` [PULL 23/26] target/riscv: rvv: Fix vslide1[up|down].vx unexpected result when XLEN=32 and SEW=64 alistair23
2025-10-03 3:27 ` [PULL 24/26] hw/riscv/riscv-iommu: Fixup PDT Nested Walk alistair23
2025-10-03 3:27 ` [PULL 25/26] target/riscv: Fix endianness swap on compressed instructions alistair23
2025-10-03 3:27 ` [PULL 26/26] docs: riscv-iommu: Update status of kernel support alistair23
2025-10-03 17:33 ` Richard Henderson [this message]
2025-10-08 14:13 ` [PULL 00/26] riscv-to-apply queue Michael Tokarev
2025-10-09 2:46 ` Alistair Francis
-- strict thread matches above, loose matches on Subject: below --
2021-10-07 6:47 Alistair Francis
2021-10-07 17:25 ` Richard Henderson
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