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[201.69.66.110]) by smtp.gmail.com with ESMTPSA id u44-20020a4a972f000000b005660ed0becesm3076144ooi.39.2023.07.04.16.11.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Jul 2023 16:12:00 -0700 (PDT) Message-ID: <9948868b-82fa-d362-2601-9bd6cc54071f@gmail.com> Date: Tue, 4 Jul 2023 20:11:57 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH] pnv/xive: Allow mmio operations of any size on the ESB CI pages Content-Language: en-US To: Frederic Barrat , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org References: <20230704144848.164287-1-fbarrat@linux.ibm.com> From: Daniel Henrique Barboza In-Reply-To: <20230704144848.164287-1-fbarrat@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c34; envelope-from=danielhb413@gmail.com; helo=mail-oo1-xc34.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 7/4/23 11:48, Frederic Barrat wrote: > We currently only allow 64-bit operations on the ESB CI pages. There's > no real reason for that limitation, skiboot/linux didn't need > more. However the hardware supports any size, so this patch relaxes > that restriction. It impacts both the ESB pages for "normal" > interrupts as well as the ESB pages for escalation interrupts defined > for the ENDs. > > Signed-off-by: Frederic Barrat > --- > > This should wrap-up the cleanup about mmio size for the xive BARs. The > NVPG and NVC BAR accesses should also be relaxed but we don't really > implement them, any load/store currently fails. Something to address > when/if we implement them. > > hw/intc/xive.c | 8 ++++---- > hw/intc/xive2.c | 4 ++-- > 2 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index f60c878345..c014e961a4 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -1175,11 +1175,11 @@ static const MemoryRegionOps xive_source_esb_ops = { > .write = xive_source_esb_write, > .endianness = DEVICE_BIG_ENDIAN, > .valid = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > .impl = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > }; > @@ -2006,11 +2006,11 @@ static const MemoryRegionOps xive_end_source_ops = { > .write = xive_end_source_write, > .endianness = DEVICE_BIG_ENDIAN, > .valid = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > .impl = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > }; > diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c > index 4d9ff41956..c37ef25d44 100644 > --- a/hw/intc/xive2.c > +++ b/hw/intc/xive2.c > @@ -954,11 +954,11 @@ static const MemoryRegionOps xive2_end_source_ops = { > .write = xive2_end_source_write, > .endianness = DEVICE_BIG_ENDIAN, > .valid = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > .impl = { > - .min_access_size = 8, > + .min_access_size = 1, > .max_access_size = 8, > }, > };