From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36891) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bKi9y-0008Bq-Gq for qemu-devel@nongnu.org; Wed, 06 Jul 2016 04:26:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bKi9t-0005vX-Eq for qemu-devel@nongnu.org; Wed, 06 Jul 2016 04:26:17 -0400 Received: from mx1.redhat.com ([209.132.183.28]:35243) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bKi9t-0005vT-6a for qemu-devel@nongnu.org; Wed, 06 Jul 2016 04:26:13 -0400 References: <20160622065624.25291-1-haozhong.zhang@intel.com> From: Laszlo Ersek Message-ID: <9999098d-ee08-8dc3-0528-d88c93b4e313@redhat.com> Date: Wed, 6 Jul 2016 10:26:08 +0200 MIME-Version: 1.0 In-Reply-To: <20160622065624.25291-1-haozhong.zhang@intel.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v5 0/4] Add QEMU support for Intel local MCE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Haozhong Zhang , qemu-devel@nongnu.org Cc: Tony Luck , rkrcmar@redhat.com, Eduardo Habkost , kvm@vger.kernel.org, "Michael S . Tsirkin" , Marcelo Tosatti , Andi Kleen , Paolo Bonzini , Ashok Raj , Boris Petkov , Richard Henderson On 06/22/16 08:56, Haozhong Zhang wrote: > Changes in v5: > * v4 Patch 1&2 are now merged into v5 Patch 1. (Paolo Bonzini) > * Add a separate Patch 3 to automatically enable LMCE for "-cpu host" > if host does support. (Eduardo Habkost) > * Move the sanity check of misconfiguration of LMCE to a separate > Patch 4. I'm fine to drop it if it's considered to be > unnecessary. (Eduardo Habkost) > * Move check of MCG_LMCE_P capability to the existing code in > kvm_arch_init_vcpu(). The difference is that if LMCE is not > supported by host but MCG_LMCE_P is included in env->mcg_cap, > kvm_arch_init_vcpu() return with error instead of just reporting a > warning. (Eduardo Habkost) > * Fix setting has_msr_feature_control in kvm_arch_init_vcpu(). (Paolo > Bonzini) > * Fix the type error in fw_cfg file "etc/msr_feature_control". >=20 > Changes in v4: > * Abort starting QEMU if lmce option is present but host does support > LMCE. (Eduardo Habkost) > * Remove setting MSR_IA32_FEATURE_CONTROL, which should be left to > guest. (Radim Kr=C4=8Dm=C3=A1, Paolo Bonzini > * Adjust error messages in mce_init(). (Boris Petkov) > * Move adding option 'lmce' to patch 1. (Eduardo Habkost, Paolo Bonzin= i) > * Adjust LMCE error message in cpu_post_load(). (Eduardo Habkost) > * (Patch 3) Add a fw_cfg file 'etc/msr_feature_control' to advise > bits should be set in MSR_IA32_FEATURE_CONTROL. (Paolo Bonzini) > * Fix SOB chain in patch 1. >=20 > Changes in v3: > * LMCE can be enabled only for non-intel guests. > * LMCE is disabled by default and a cpu option 'lmce=3Don/off' is adde= d > to explicitly enable/disable LMCE. > * LMCE is disabled if KVM does not support (even though 'lmce=3Don'). > * VM on LMCE-enabled QEMU can be only migrated to LMCE-enabled QEMU. > * MCG_LMCE_P is not included in MCE_CAP_DEF and instead added to > env->mcg_cap if LMCE is enabled. > * Code style fix. >=20 > This QEMU patch series along with the corresponding KVM patch series > (sent via another email with title "[PATCH v3 0/3] Add KVM support for > Intel local MCE") enables Intel local MCE feature for guest. >=20 > Intel Local MCE (LMCE) is a feature on Intel Skylake Server CPU that > can deliver MCE to a single processor thread instead of broadcasting > to all threads, which can reduce software's load when processing MCE > on machines with a large number of processor threads. >=20 > The technical details of LMCE can be found in Intel SDM Vol 3, Chapter > "Machine-Check Architecture" (search for 'LMCE'). Basically, > * The capability of LMCE is indicated by bit 27 (MCG_LMCE_P) of > MSR_IA32_MCG_CAP. > * LMCE is enabled by setting bit 20 (MSR_IA32_FEATURE_CONTROL_LMCE) > of MSR_IA32_FEATURE_CONTROL and bit 0 (MCG_EXT_CTL_LMCE_EN) of > MSR_IA32_MCG_EXT_CTL. > * Software can determine if a MCE is local to the current processor > thread by checking bit 2 (MCG_STATUS_LMCE) of MSR_IA32_MCG_STATUS. >=20 > Ashok Raj (1): > target-i386: KVM: add basic Intel LMCE support >=20 > Haozhong Zhang (3): > i386: publish advised value of MSR_IA32_FEATURE_CONTROL via fw_cfg > target-i386: enable LMCE for '-cpu host' if supported by host > target-i386: abort migration if LMCE config mismatch >=20 > hw/i386/pc.c | 29 +++++++++++++++++++++++++++++ > target-i386/cpu.c | 19 ++++++++++++++++++- > target-i386/cpu.h | 16 ++++++++++++++++ > target-i386/kvm.c | 36 +++++++++++++++++++++++++++++++++--- > target-i386/machine.c | 25 +++++++++++++++++++++++++ > 5 files changed, 121 insertions(+), 4 deletions(-) >=20 How can I test this series? I'm trying to satisfy the conditions in pc_build_feature_control_file(), = so that "etc/msr_feature_control" is created. However, I cannot even trig= ger if (ecx & CPUID_EXT_VMX) { feature_control_bits |=3D FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_S= MX; } I tried various -cpu switches (with and without -enable-kvm); nothing see= ms to work. When I add "+vmx", QEMU always complains that vmx is not avai= lable. Any hints? (My laptop does support VMX, and it has FEATURE_CONTROL_VMXON_ENABLED_OUT= SIDE_SMX set in the corresponding host MSR.) Thanks Laszlo