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[68.185.11.182]) by smtp.gmail.com with ESMTPSA id g1sm954534pjt.40.2020.11.09.19.24.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Nov 2020 19:24:30 -0800 (PST) Subject: Re: [PATCH] ppc/translate: Fix unordered f64/f128 comparisons To: LemonBoy , qemu-devel@nongnu.org References: <20201109102147.31747-1-thatlemon@gmail.com> From: Richard Henderson Message-ID: <99c83004-82ef-882b-b41d-a163b0966aa4@linaro.org> Date: Mon, 9 Nov 2020 19:24:27 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201109102147.31747-1-thatlemon@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/9/20 2:21 AM, LemonBoy wrote: > According to the PowerISA v3.1 reference, Table 68 "Actions for xscmpudp > - Part 1: Compare Unordered", whenever one of the two operands is a NaN > the SO bit is set while the other three bits are cleared. > > Apply the same change to xscmpuqp. > > The respective ordered counterparts are unaffected. > > Signed-off-by: Giuseppe Musacchio > --- > target/ppc/fpu_helper.c | 32 ++++++++++++++++++++++---------- > 1 file changed, 22 insertions(+), 10 deletions(-) > > diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c > index 9b8c8b70b6..b07ff66375 100644 > --- a/target/ppc/fpu_helper.c > +++ b/target/ppc/fpu_helper.c > @@ -2479,13 +2479,11 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, \ > if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \ > float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \ > vxsnan_flag = true; \ > - cc = CRF_SO; \ > if (fpscr_ve == 0 && ordered) { \ > vxvc_flag = true; \ > } \ > } else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) || \ > float64_is_quiet_nan(xb->VsrD(0), &env->fp_status)) { \ > - cc = CRF_SO; \ > if (ordered) { \ > vxvc_flag = true; \ > } \ > @@ -2497,12 +2495,19 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, \ > float_invalid_op_vxvc(env, 0, GETPC()); \ > } \ > \ > - if (float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) { \ > + switch (float64_compare(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) {\ > + case float_relation_less: \ > cc |= CRF_LT; \ > - } else if (!float64_le(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) { \ > - cc |= CRF_GT; \ > - } else { \ > + break; \ > + case float_relation_equal: \ > cc |= CRF_EQ; \ > + break; \ > + case float_relation_greater: \ > + cc |= CRF_GT; \ > + break; \ > + case float_relation_unordered: \ > + cc |= CRF_SO; \ > + break; \ > } This needs some more cleanup. There's no point in checking for nans first; wait until you get to float_relation_unordered. These macros should be made into straight functions. r~