From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A971FC48297 for ; Fri, 9 Feb 2024 08:32:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rYMIk-0004p4-G2; Fri, 09 Feb 2024 03:32:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rYMIj-0004od-8m; Fri, 09 Feb 2024 03:32:01 -0500 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3] helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rYMIh-0001Wd-0m; Fri, 09 Feb 2024 03:32:01 -0500 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4TWRsc62Xbz4x2N; Fri, 9 Feb 2024 19:31:48 +1100 (AEDT) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4TWRsZ5VtQz4wcm; Fri, 9 Feb 2024 19:31:46 +1100 (AEDT) Message-ID: <99e302b1-d24d-452e-87d0-ff7f47bc566f@kaod.org> Date: Fri, 9 Feb 2024 09:31:41 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] aspeed: fix hardcode boot address 0 Content-Language: en-US To: Jamin Lin , Peter Maydell , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" Cc: troy_lee@aspeedtech.com References: <20240207195224.452987-1-jamin_lin@aspeedtech.com> <20240207195224.452987-3-jamin_lin@aspeedtech.com> From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= In-Reply-To: <20240207195224.452987-3-jamin_lin@aspeedtech.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=vk+A=JS=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -39 X-Spam_score: -4.0 X-Spam_bar: ---- X-Spam_report: (-4.0 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/7/24 20:52, Jamin Lin wrote: > In the previous design of ASPEED SOCs QEMU model, it set the boot > address at "0" which was the hardcode setting for ast10x0, ast2600, > ast2500 and ast2400. > > According to the design of ast2700, it has bootmcu which is used for > executing SPL and initialize DRAM, then, CPUs(cortex-a35) > execute u-boot, kernel and rofs. QEMU will only support CPU(cortex-a35) > parts and the boot address is "0x4 00000000" for ast2700. > Therefore, fixed hardcode boot address 0. > > Signed-off-by: Troy Lee > Signed-off-by: Jamin Lin I agree with Philippe that the justification could be simpler. This change is just a cleanup preparing ground for future models using a different mapping address. Reviewed-by: Cédric Le Goater Thanks, C. > --- > hw/arm/aspeed.c | 4 +++- > hw/arm/aspeed_ast2400.c | 4 ++-- > hw/arm/aspeed_ast2600.c | 2 +- > include/hw/arm/aspeed_soc.h | 2 -- > 4 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 06d863958b..39758557be 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -289,12 +289,14 @@ static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, > uint64_t rom_size) > { > AspeedSoCState *soc = bmc->soc; > + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc); > > memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, > &error_abort); > memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, > &bmc->boot_rom, 1); > - write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort); > + write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], > + rom_size, &error_abort); > } > > void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, > diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c > index 95da85fee0..d125886207 100644 > --- a/hw/arm/aspeed_ast2400.c > +++ b/hw/arm/aspeed_ast2400.c > @@ -26,7 +26,7 @@ > #define ASPEED_SOC_IOMEM_SIZE 0x00200000 > > static const hwaddr aspeed_soc_ast2400_memmap[] = { > - [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR, > + [ASPEED_DEV_SPI_BOOT] = 0x00000000, > [ASPEED_DEV_IOMEM] = 0x1E600000, > [ASPEED_DEV_FMC] = 0x1E620000, > [ASPEED_DEV_SPI1] = 0x1E630000, > @@ -61,7 +61,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = { > }; > > static const hwaddr aspeed_soc_ast2500_memmap[] = { > - [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR, > + [ASPEED_DEV_SPI_BOOT] = 0x00000000, > [ASPEED_DEV_IOMEM] = 0x1E600000, > [ASPEED_DEV_FMC] = 0x1E620000, > [ASPEED_DEV_SPI1] = 0x1E630000, > diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c > index f74561ecdc..174be53770 100644 > --- a/hw/arm/aspeed_ast2600.c > +++ b/hw/arm/aspeed_ast2600.c > @@ -22,7 +22,7 @@ > #define ASPEED_SOC_DPMCU_SIZE 0x00040000 > > static const hwaddr aspeed_soc_ast2600_memmap[] = { > - [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR, > + [ASPEED_DEV_SPI_BOOT] = 0x00000000, > [ASPEED_DEV_SRAM] = 0x10000000, > [ASPEED_DEV_DPMCU] = 0x18000000, > /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h > index 5ab0902da0..bf43ad8351 100644 > --- a/include/hw/arm/aspeed_soc.h > +++ b/include/hw/arm/aspeed_soc.h > @@ -224,8 +224,6 @@ enum { > ASPEED_DEV_FSI2, > }; > > -#define ASPEED_SOC_SPI_BOOT_ADDR 0x0 > - > qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); > bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); > void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr);