From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>, peter.maydell@linaro.org
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com,
palmer@dabbelt.com, alistair23@gmail.com, alex.bennee@linaro.org
Subject: Re: [RFC PATCH 8/8] riscv: Add RV64F instructions description
Date: Mon, 11 May 2020 11:11:31 -0700 [thread overview]
Message-ID: <99fa418c-9a2e-d806-b164-3a08fecd74e8@linaro.org> (raw)
In-Reply-To: <20200430072139.4602-9-zhiwei_liu@c-sky.com>
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> +FCVT_L_S RISCV 1100000 00010 rs1:5 rm:3 rd:5 1010011 \
> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
> +
> +FCVT_LU_S RISCV 1100000 00011 rs1:5 rm:3 rd:5 1010011 \
> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
> +
> +FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \
> +!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
> +
> +FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \
> +!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
Interesting question here: Do we really want to avoid the reserved rounding
modes, or do we want to verify that we raise an invalid operand exception?
I guess I'm fine with it either way.
r~
next prev parent reply other threads:[~2020-05-11 18:12 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-30 7:21 [RFC PATCH 0/8] RISCV risu porting LIU Zhiwei
2020-04-30 7:21 ` [RFC PATCH 1/8] riscv: Add RV64I instructions description LIU Zhiwei
2020-05-11 16:39 ` Richard Henderson
2020-05-20 2:41 ` LIU Zhiwei
2020-05-20 5:39 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 2/8] riscv: Generate payload scripts LIU Zhiwei
2020-05-11 17:40 ` Richard Henderson
2020-05-20 2:37 ` LIU Zhiwei
2020-05-20 5:41 ` Richard Henderson
2020-05-20 9:06 ` LIU Zhiwei
2020-04-30 7:21 ` [RFC PATCH 3/8] riscv: Define riscv struct reginfo LIU Zhiwei
2020-05-11 17:42 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 4/8] riscv: Implement payload load interfaces LIU Zhiwei
2020-05-11 18:03 ` Richard Henderson
2020-05-11 18:07 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 5/8] riscv: Add standard test case LIU Zhiwei
2020-05-11 18:04 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 6/8] riscv: Add configure script LIU Zhiwei
2020-05-11 18:06 ` Richard Henderson
2020-05-20 1:45 ` LIU Zhiwei
2020-05-20 2:28 ` LIU Zhiwei
2020-04-30 7:21 ` [RFC PATCH 7/8] riscv: Add RV64M instructions description LIU Zhiwei
2020-05-11 18:12 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 8/8] riscv: Add RV64F " LIU Zhiwei
2020-05-11 18:11 ` Richard Henderson [this message]
2020-05-19 12:27 ` LIU Zhiwei
2020-05-11 16:30 ` [RFC PATCH 0/8] RISCV risu porting Richard Henderson
2020-05-19 9:44 ` LIU Zhiwei
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