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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id d184sm9571351pfc.130.2020.05.11.11.11.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 May 2020 11:11:33 -0700 (PDT) Subject: Re: [RFC PATCH 8/8] riscv: Add RV64F instructions description To: LIU Zhiwei , peter.maydell@linaro.org References: <20200430072139.4602-1-zhiwei_liu@c-sky.com> <20200430072139.4602-9-zhiwei_liu@c-sky.com> From: Richard Henderson Message-ID: <99fa418c-9a2e-d806-b164-3a08fecd74e8@linaro.org> Date: Mon, 11 May 2020 11:11:31 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20200430072139.4602-9-zhiwei_liu@c-sky.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, palmer@dabbelt.com, alistair23@gmail.com, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 4/30/20 12:21 AM, LIU Zhiwei wrote: > +FCVT_L_S RISCV 1100000 00010 rs1:5 rm:3 rd:5 1010011 \ > +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 } > + > +FCVT_LU_S RISCV 1100000 00011 rs1:5 rm:3 rd:5 1010011 \ > +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 } > + > +FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \ > +!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 } > + > +FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \ > +!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 } Interesting question here: Do we really want to avoid the reserved rounding modes, or do we want to verify that we raise an invalid operand exception? I guess I'm fine with it either way. r~