From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Mohamed Mediouni <mohamed@unpredictable.fr>, qemu-devel@nongnu.org
Cc: Mads Ynddal <mads@ynddal.dk>, Paolo Bonzini <pbonzini@redhat.com>,
Shannon Zhao <shannon.zhaosl@gmail.com>,
Phil Dennis-Jordan <phil@philjordan.eu>,
Igor Mammedov <imammedo@redhat.com>,
qemu-arm@nongnu.org, Alexander Graf <agraf@csgraf.de>,
Roman Bolshakov <rbolshakov@ddn.com>,
Peter Maydell <peter.maydell@linaro.org>,
"Michael S. Tsirkin" <mst@redhat.com>,
Ani Sinha <anisinha@redhat.com>,
Cameron Esfahani <dirty@apple.com>
Subject: Re: [PATCH v5 11/13] hvf: gate ARM_FEATURE_PMU register emulation behind not being at EL2
Date: Wed, 6 Aug 2025 13:21:38 +0200 [thread overview]
Message-ID: <9a445a3b-df8d-4cfd-8561-5295ad6fd30b@linaro.org> (raw)
In-Reply-To: <20250728134114.77545-12-mohamed@unpredictable.fr>
On 28/7/25 15:41, Mohamed Mediouni wrote:
> From Apple documentation:
>
>> When EL2 is disabled, PMU register accesses trigger "Trapped MSR, MRS, or
>> System Instruction" exceptions. When this happens, hv_vcpu_run() returns, and the
>> hv_vcpu_exit_t object contains the information about this exception.
>
>> When EL2 is enabled, the handling of PMU register accesses is determined by the PMUVer
>> field of ID_AA64DFR0_EL1 register.
>> If the PMUVer field value is zero or is invalid, PMU register accesses generate "Undefined"
>> exceptions, which are sent to the guest.
>> If the PMUVer field value is non-zero and valid, PMU register accesses are emulated by the framework.
>> The ID_AA64DFR0_EL1 register can be modified via hv_vcpu_set_sys_reg API.
>
> Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
> ---
> target/arm/hvf/hvf.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2025-08-06 11:22 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-28 13:41 [PATCH v5 00/13] HVF: Add support for platform vGIC and nested virtualisation Mohamed Mediouni
2025-07-28 13:41 ` [PATCH v5 01/13] hvf: switch hvf_arm_get_host_cpu_features to not create a vCPU Mohamed Mediouni
2025-08-06 11:12 ` Philippe Mathieu-Daudé
2025-07-28 13:41 ` [PATCH v5 02/13] accel, hw/arm, include/system/hvf: infrastructure changes for HVF vGIC Mohamed Mediouni
2025-08-06 11:32 ` Philippe Mathieu-Daudé
2025-08-07 2:03 ` Mohamed Mediouni
2025-07-28 13:41 ` [PATCH v5 03/13] hw/intc: Add hvf vGIC interrupt controller support Mohamed Mediouni
2025-08-06 10:32 ` Philippe Mathieu-Daudé
2025-07-28 13:41 ` [PATCH v5 04/13] hw/arm, target/arm: nested virtualisation on HVF Mohamed Mediouni
2025-07-28 13:41 ` [PATCH v5 05/13] hvf: save/restore Apple GIC state Mohamed Mediouni
2025-07-28 13:41 ` [PATCH v5 06/13] target/arm: hvf: pass through CNTHCTL_EL2 and MDCCINT_EL1 Mohamed Mediouni
2025-08-06 11:20 ` Philippe Mathieu-Daudé
2025-08-11 10:08 ` Mads Ynddal
2025-08-11 10:22 ` Peter Maydell
2025-08-12 11:29 ` Mads Ynddal
2025-07-28 13:41 ` [PATCH v5 07/13] hw/arm: virt: add GICv2m for the case when ITS is not available Mohamed Mediouni
2025-07-28 13:41 ` [PATCH v5 08/13] hw/arm: virt: cleanly fail on attempt to use the platform vGIC together with ITS Mohamed Mediouni
2025-07-28 13:41 ` [PATCH v5 09/13] hvf: only call hvf_sync_vtimer() when running without the platform vGIC Mohamed Mediouni
2025-07-28 13:41 ` [PATCH v5 10/13] hvf: sync registers used at EL2 Mohamed Mediouni
2025-08-06 11:10 ` Philippe Mathieu-Daudé
2025-07-28 13:41 ` [PATCH v5 11/13] hvf: gate ARM_FEATURE_PMU register emulation behind not being " Mohamed Mediouni
2025-08-06 11:21 ` Philippe Mathieu-Daudé [this message]
2025-07-28 13:41 ` [PATCH v5 12/13] target/arm: hvf: instantiate GIC early Mohamed Mediouni
2025-07-28 13:41 ` [PATCH v5 13/13] target/arm: hvf: add asserts for code paths not leveraged when using the vGIC Mohamed Mediouni
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