Re: [PATCH v3 16/16] target/mips: Convert nanoMIPS LI opcodes to decodetree

[Richard Henderson <richard.henderson@linaro.org>]

On 11/26/24 08:00, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/mips/tcg/nanomips16.decode        |  8 ++++++++
>   target/mips/tcg/nanomips48.decode        |  8 ++++++++
>   target/mips/tcg/nanomips_translate.c     | 21 +++++++++++++++++++++
>   target/mips/tcg/nanomips_translate.c.inc | 17 -----------------
>   4 files changed, 37 insertions(+), 17 deletions(-)
> 
> diff --git a/target/mips/tcg/nanomips16.decode b/target/mips/tcg/nanomips16.decode
> index 81fdc68e98b..12815161d9c 100644
> --- a/target/mips/tcg/nanomips16.decode
> +++ b/target/mips/tcg/nanomips16.decode
> @@ -6,3 +6,11 @@
>   #
>   # Reference: nanoMIPS32 Instruction Set Technical Reference Manual
>   #            (Document Number: MD01247)
> +
> +&rd_imm             rd imm not_in_nms
> +
> +%s_eu               0:s7 !function=s_eu
> +
> +@rt3_s          ...... rd:3 .......         &rd_imm         imm=%s_eu
> +
> +LI              110100 ... .......          @rt3_s          not_in_nms=0        # LI[16]

I think probably it is a mistake to include not_in_nms in the argument set.
I think it would be better to have separate trans_LI and trans_LI_nnms.


> diff --git a/target/mips/tcg/nanomips48.decode b/target/mips/tcg/nanomips48.decode
> index 696cc15607a..778bff4ec06 100644
> --- a/target/mips/tcg/nanomips48.decode
> +++ b/target/mips/tcg/nanomips48.decode
> @@ -6,3 +6,11 @@
>   #
>   # Reference: nanoMIPS32 Instruction Set Technical Reference Manual
>   #            (Document Number: MD01247)
> +
> +&rd_imm     rd  imm not_in_nms                                       !extern
> +
> +%imm        16:16 0:s16

These subfields are swapped.

That said...  I will note that all 48-bit instructions are 16-bit plus a 32-bit immediate. 
There's a trick we used over in target/rx/ where we (ab)use !function to read immediate 
data. Using this would mean that we can treat all of these 48-bit insns as 16-bit insns.

%i48       !func=i48
@ri48      ...... rt:5  .....  &ri imm=%i48

LI_nnmi    011000 ..... 00000  @ri48


r~