From: "Cédric Le Goater" <clg@kaod.org>
To: Yubin Zou <yubinz@google.com>, <qemu-devel@nongnu.org>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Steven Lee <steven_lee@aspeedtech.com>,
Troy Lee <leetroy@gmail.com>,
Jamin Lin <jamin_lin@aspeedtech.com>,
Andrew Jeffery <andrew@codeconstruct.com.au>,
Joel Stanley <joel@jms.id.au>, Fabiano Rosas <farosas@suse.de>,
Laurent Vivier <lvivier@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Kane-Chen-AS <kane_chen@aspeedtech.com>,
Nabih Estefan <nabihestefan@google.com>, <qemu-arm@nongnu.org>
Subject: Re: [PATCH v2 4/6] hw/arm/aspeed_soc: Update Aspeed SoC to support two SGPIO controllers
Date: Tue, 9 Dec 2025 17:15:04 +0100 [thread overview]
Message-ID: <9a5fe690-92f7-4745-995d-01c93cefeef9@kaod.org> (raw)
In-Reply-To: <20251209-aspeed-sgpio-v2-4-976e5f5790c2@google.com>
On 12/9/25 01:01, Yubin Zou wrote:
> This commit updates the Aspeed SoC model to support two SGPIO
> controllers, reflecting the hardware capabilities of the AST2700
>
> The memory map and interrupt map are updated to include entries for
> two SGPIO controllers (SGPIOM0 and SGPIOM1). This change is a
> prerequisite for the full implementation of the SGPIO device model.
>
> Signed-off-by: Yubin Zou <yubinz@google.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> hw/arm/aspeed_ast10x0.c | 6 +++---
> hw/arm/aspeed_ast27x0.c | 10 ++++++++++
> include/hw/arm/aspeed_soc.h | 8 ++++++--
> 3 files changed, 19 insertions(+), 5 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index 7f49c13391be0b923e317409a0fccfa741f5e658..c141cc080422579ca6b6965369d84dfbe416247b 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -36,7 +36,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
> [ASPEED_DEV_ESPI] = 0x7E6EE000,
> [ASPEED_DEV_SBC] = 0x7E6F2000,
> [ASPEED_DEV_GPIO] = 0x7E780000,
> - [ASPEED_DEV_SGPIOM] = 0x7E780500,
> + [ASPEED_DEV_SGPIOM0] = 0x7E780500,
> [ASPEED_DEV_TIMER1] = 0x7E782000,
> [ASPEED_DEV_UART1] = 0x7E783000,
> [ASPEED_DEV_UART2] = 0x7E78D000,
> @@ -94,7 +94,7 @@ static const int aspeed_soc_ast1030_irqmap[] = {
> [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
> [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
> [ASPEED_DEV_UDC] = 9,
> - [ASPEED_DEV_SGPIOM] = 51,
> + [ASPEED_DEV_SGPIOM0] = 51,
> [ASPEED_DEV_JTAG0] = 27,
> [ASPEED_DEV_JTAG1] = 53,
> };
> @@ -427,7 +427,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
> sc->memmap[ASPEED_DEV_UDC], 0x1000);
> aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->sgpiom),
> "aspeed.sgpiom",
> - sc->memmap[ASPEED_DEV_SGPIOM], 0x100);
> + sc->memmap[ASPEED_DEV_SGPIOM0], 0x100);
>
> aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[0]),
> "aspeed.jtag",
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index c484bcd4e22fb49faf9c16992ae2cdfd6cd82da4..e5f04bd16e80696e41005d9062a6df6d060b8088 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -69,6 +69,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_ADC] = 0x14C00000,
> [ASPEED_DEV_SCUIO] = 0x14C02000,
> [ASPEED_DEV_GPIO] = 0x14C0B000,
> + [ASPEED_DEV_SGPIOM0] = 0x14C0C000,
> + [ASPEED_DEV_SGPIOM1] = 0x14C0D000,
> [ASPEED_DEV_I2C] = 0x14C0F000,
> [ASPEED_DEV_INTCIO] = 0x14C18000,
> [ASPEED_DEV_PCIE_PHY2] = 0x14C1C000,
> @@ -122,6 +124,8 @@ static const int aspeed_soc_ast2700a0_irqmap[] = {
> [ASPEED_DEV_KCS] = 128,
> [ASPEED_DEV_ADC] = 130,
> [ASPEED_DEV_GPIO] = 130,
> + [ASPEED_DEV_SGPIOM0] = 130,
> + [ASPEED_DEV_SGPIOM1] = 130,
> [ASPEED_DEV_I2C] = 130,
> [ASPEED_DEV_FMC] = 131,
> [ASPEED_DEV_WDT] = 131,
> @@ -173,6 +177,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {
> [ASPEED_DEV_I2C] = 194,
> [ASPEED_DEV_ADC] = 194,
> [ASPEED_DEV_GPIO] = 194,
> + [ASPEED_DEV_SGPIOM0] = 194,
> + [ASPEED_DEV_SGPIOM1] = 194,
> [ASPEED_DEV_FMC] = 195,
> [ASPEED_DEV_WDT] = 195,
> [ASPEED_DEV_PWM] = 195,
> @@ -214,6 +220,8 @@ static const int ast2700_gic130_gic194_intcmap[] = {
> [ASPEED_DEV_I2C] = 0,
> [ASPEED_DEV_ADC] = 16,
> [ASPEED_DEV_GPIO] = 18,
> + [ASPEED_DEV_SGPIOM0] = 21,
> + [ASPEED_DEV_SGPIOM1] = 24,
> };
>
> /* GICINT 131 */
> @@ -1061,6 +1069,7 @@ static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, const void *data)
> sc->sram_size = 0x20000;
> sc->pcie_num = 0;
> sc->spis_num = 3;
> + sc->sgpio_num = 2;
> sc->ehcis_num = 2;
> sc->wdts_num = 8;
> sc->macs_num = 1;
> @@ -1089,6 +1098,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
> sc->sram_size = 0x20000;
> sc->pcie_num = 3;
> sc->spis_num = 3;
> + sc->sgpio_num = 2;
> sc->ehcis_num = 4;
> sc->wdts_num = 8;
> sc->macs_num = 3;
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 4b8e599f1a53bfb2e4d3196d5495cd316f799354..18ff961a38508c5df83b46e187f732d736443f20 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -32,6 +32,7 @@
> #include "hw/net/ftgmac100.h"
> #include "target/arm/cpu.h"
> #include "hw/gpio/aspeed_gpio.h"
> +#include "hw/gpio/aspeed_sgpio.h"
> #include "hw/sd/aspeed_sdhci.h"
> #include "hw/usb/hcd-ehci.h"
> #include "qom/object.h"
> @@ -46,6 +47,7 @@
> #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
>
> #define ASPEED_SPIS_NUM 3
> +#define ASPEED_SGPIO_NUM 2
> #define ASPEED_EHCIS_NUM 4
> #define ASPEED_WDTS_NUM 8
> #define ASPEED_CPUS_NUM 4
> @@ -89,6 +91,7 @@ struct AspeedSoCState {
> AspeedMiiState mii[ASPEED_MACS_NUM];
> AspeedGPIOState gpio;
> AspeedGPIOState gpio_1_8v;
> + AspeedSGPIOState sgpiom[ASPEED_SGPIO_NUM];
> AspeedSDHCIState sdhci;
> AspeedSDHCIState emmc;
> AspeedLPCState lpc;
> @@ -106,7 +109,6 @@ struct AspeedSoCState {
> UnimplementedDeviceState pwm;
> UnimplementedDeviceState espi;
> UnimplementedDeviceState udc;
> - UnimplementedDeviceState sgpiom;
> UnimplementedDeviceState ltpi;
> UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
> AspeedAPB2OPBState fsi[2];
> @@ -166,6 +168,7 @@ struct AspeedSoCClass {
> uint64_t secsram_size;
> int pcie_num;
> int spis_num;
> + int sgpio_num;
> int ehcis_num;
> int wdts_num;
> int macs_num;
> @@ -221,6 +224,8 @@ enum {
> ASPEED_DEV_SDHCI,
> ASPEED_DEV_GPIO,
> ASPEED_DEV_GPIO_1_8V,
> + ASPEED_DEV_SGPIOM0,
> + ASPEED_DEV_SGPIOM1,
> ASPEED_DEV_RTC,
> ASPEED_DEV_TIMER1,
> ASPEED_DEV_TIMER2,
> @@ -263,7 +268,6 @@ enum {
> ASPEED_DEV_I3C,
> ASPEED_DEV_ESPI,
> ASPEED_DEV_UDC,
> - ASPEED_DEV_SGPIOM,
> ASPEED_DEV_JTAG0,
> ASPEED_DEV_JTAG1,
> ASPEED_DEV_FSI1,
>
next prev parent reply other threads:[~2025-12-09 16:15 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-09 0:01 [PATCH v2 0/6] hw/gpio/aspeed_sgpio: Add Aspeed Serial GPIO (SGPIO) controller model Yubin Zou
2025-12-09 0:01 ` [PATCH v2 1/6] hw/gpio/aspeed_sgpio: Add basic device model for Aspeed SGPIO Yubin Zou
2025-12-09 9:22 ` Cédric Le Goater
2025-12-10 8:02 ` Yubin Zou
2025-12-09 0:01 ` [PATCH v2 2/6] hw/gpio/aspeed_sgpio: aspeed: Add QOM property accessors for SGPIO pins Yubin Zou
2025-12-09 14:52 ` Cédric Le Goater
2025-12-10 8:08 ` Yubin Zou
2025-12-09 0:01 ` [PATCH v2 3/6] hw/gpio/aspeed_sgpio: Implement SGPIO interrupt handling Yubin Zou
2025-12-09 0:01 ` [PATCH v2 4/6] hw/arm/aspeed_soc: Update Aspeed SoC to support two SGPIO controllers Yubin Zou
2025-12-09 16:15 ` Cédric Le Goater [this message]
2025-12-09 0:01 ` [PATCH v2 5/6] hw/arm/aspeed_ast27x0: Wire SGPIO controller to AST2700 SoC Yubin Zou
2025-12-09 16:15 ` Cédric Le Goater
2025-12-09 0:01 ` [PATCH v2 6/6] test/qtest: Add Unit test for Aspeed SGPIO Yubin Zou
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