Re: [Qemu-devel] [PATCH v2 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree

[Richard Henderson <richard.henderson@linaro.org>]

On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> --- a/target/riscv/insn_trans/trans_rvc.inc.c
> +++ b/target/riscv/insn_trans/trans_rvc.inc.c
> @@ -23,8 +23,7 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a,
>  {
>      if (a->nzuimm == 0) {
>          /* Reserved in ISA */
> -        gen_exception_illegal(ctx);
> -        return true;
> +        return false;

Ah, the change for patch 16 got squished to the wrong patch.

> +static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a, uint16_t insn)
> +{
> +    int shamt = a->shamt;
> +    if (shamt == 0) {
> +        /* For RV128 a shamt of 0 means a shift by 64 */
> +        shamt = 64;
> +    }
> +    /* Ensure, that shamt[5] is zero for RV32 */
> +    if (shamt >= TARGET_LONG_BITS) {
> +        return false;
> +    }
> +
> +    arg_srli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
> +    return trans_srli(ctx, &arg, insn);
> +}
> +
> +static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a, uint16_t insn)
> +{
> +    if (a->shamt == 0) {
> +        /* Reserved in ISA */
> +        return false;
> +    }
> +#ifdef TARGET_RISCV32
> +    /* Ensure, that shamt[5] is zero for RV32 */
> +    if (a->shamt >= 32) {
> +        return false;
> +    }
> +#endif

Same change as srli.  Otherwise,

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~