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Wed, 27 Nov 2024 15:03:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IGEFPvcSRcdt27+r9AKdZQMAP/ep7Xe7LOkxD0twjxGQ6lgrTqjek+6BBIEKJ0q4COQyfIBKg== X-Received: by 2002:a05:6e02:3312:b0:3a7:c5b1:a55f with SMTP id e9e14a558f8ab-3a7c5b1a78bmr45534515ab.0.1732748626403; Wed, 27 Nov 2024 15:03:46 -0800 (PST) Received: from [192.168.40.164] ([70.105.235.240]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4e230e5ec80sm14862173.86.2024.11.27.15.03.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Nov 2024 15:03:45 -0800 (PST) Message-ID: <9a62fa8d-a7a0-4bc1-bccb-2fcfaa119d65@redhat.com> Date: Wed, 27 Nov 2024 18:03:23 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 2/5] hw/arm/smmuv3: Add initial support for SMMUv3 Nested device Content-Language: en-US To: Jason Gunthorpe , Shameerali Kolothum Thodi Cc: Nicolin Chen , Eric Auger , "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , Linuxarm , "Wangzhou (B)" , jiangkunkun , Jonathan Cameron , "zhangfei.gao@linaro.org" References: <20241108125242.60136-1-shameerali.kolothum.thodi@huawei.com> <20241108125242.60136-3-shameerali.kolothum.thodi@huawei.com> <00e8a5d6-c926-44bb-8d11-dab4ddc4820d@redhat.com> <20241127160031.GA1253388@nvidia.com> From: Donald Dutile In-Reply-To: <20241127160031.GA1253388@nvidia.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=ddutile@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/27/24 11:00 AM, Jason Gunthorpe wrote: > On Wed, Nov 27, 2024 at 10:21:24AM +0000, Shameerali Kolothum Thodi wrote: >>> For SMMUv3, NVIDIA-specific vCMDQ, it needs a parameter to state that >>> specifically, >>> since I'm concluding from reading the SMMUv3 version G.a spec, that >>> ECMDQ was added >>> to be able to assign an ECMDQ to a VM, >> >> Not sure the intention of ECMDQ as per that specification is to assign >> it to a VM. I think the main idea behind it is to have one Command Queue >> per host CPU to eliminate lock contention while submitting commands >> to SMMU. > > Right > >> AFAIK it is not safe to assign one of the ECMDQ to guest yet. I think there is no >> way you can associate a VMID with ECMDQ. So there is no plan to >> support ARM ECMDQ now. > > Yep > 'Yet' ... The association would be done via the VMM -- no different then what associates an assigned device to a VM today -- no hw-level (VM-)ID needed; a matter of exposing it to the VM, or not; or mapping the (virtual) CMDQ to the mapped/associated ECMDQ. They are purposedly mapped 64K apart from each other, enabling page-level protection, which I doubt is a per-CPU req for lock contention avoidance (large-cache-block spaced would be sufficient, even 4k; it's 64k spaced btwn ECMDQ regs .. the largest ARM page size. Summary: let's not assume this can't happen, and the chosen cmdline prevents it. >> NVIDIA VCMDQ is a completely vendor specific one. Perhaps ARM may come >> up with an assignable CMDQ in future though. > > Yes, it is easy to imagine an ECMDQ extension that provides the same HW > features that VCMDQ has in future. I hope ARM will develop one. > Right, so how to know what op is being "accel"'d wrt smmuv3. >>> ... and all needs to be per-instance .... >>> ... libvirt (or any other VMM orchestrator) will need to determine >>> compatibility for >>> live migration. e.g., can one live migrate an accel=nv-vcmdq-based VM to >>> a host with >>> accel=ecmdq support? only nv-vcmdq? what if there are version diffs of >>> nv-vcmdq over time? >>> -- apologies, but I don't know the minute details of nv-vcmdq to >>> determine if that's unlikely or not. >> >> Yes. This require more thought. But our first aim is get the basic smmuv3-accel >> support. > > Yeah, there is no live migration support yet in the SMMU qmeu driver, > AFAIK? > > When it gets done the supported options will have to be considered > > Jason >