Re: [Qemu-devel] [PATCH v3 1/2] ppc: Add support for 'mffscrn', 'mffscrni' instructions

[Richard Henderson <richard.henderson@linaro.org>]

On 9/18/19 7:31 AM, Paul A. Clarke wrote:
> From: "Paul A. Clarke" <pc@us.ibm.com>
> 
> ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
> instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
> This patch adds support for 'mffscrn' and 'mffscrni' instructions.
> 
> 'mffscrn' and 'mffscrni' are similar to 'mffsl', except they do not return
> the status bits (FI, FR, FPRF) and they also set the rounding mode in the
> FPSCR.
> 
> On CPUs without support for 'mffscrn'/'mffscrni' (below ISA 3.0), the
> instructions will execute identically to 'mffs'.
> 
> Signed-off-by: Paul A. Clarke <pc@us.ibm.com>
> ---
> v3:
> - Fix v2 change which cleared inadvertently clearned DRN.
> - Remove FP_MODE, use FP_DRN and FP_RN explicitly instead.
> - I did not remove the FPSCR_DRN[012] or FP_DRN[012] defines, as it's
>   clearer to me that it's a 3-bit field, but am happy to respin if that
>   is preferred.
> v2:
> - Add DRN to returned FPSCR value.
> - Add DRN defines to target/ppc/cpu.h.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~