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Thu, 15 May 2025 15:52:16 +0000 (GMT) Message-ID: <9a96117a19da549a17c0dc12d232fdbc86b64496.camel@linux.ibm.com> Subject: Re: [PATCH 20/50] pnv/xive2: Permit valid writes to VC/PC Flush Control registers From: Miles Glenn To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, =?ISO-8859-1?Q?Fr=E9d=E9ric?= Barrat , Michael Kowal , Caleb Schlossin Date: Thu, 15 May 2025 10:52:15 -0500 In-Reply-To: <20250512031100.439842-21-npiggin@gmail.com> References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-21-npiggin@gmail.com> Organization: IBM Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-27.el8_10) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=Cf0I5Krl c=1 sm=1 tr=0 ts=68260db3 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VnNF1IyMAAAA:8 a=K43VmlK4zf_02HQK-ZgA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE1NSBTYWx0ZWRfXybcaOAQwMJUf CoTMnnUWjwsU0izEPMdBwBesmFTuKG/8yUquCncPNRu0zzZPO8S+hxc15TatzDdM1BJ72+NefWa wbc5t37PEkDps4BEiIfdyguXsKYrkmXpPT5BMq9R2T7pFJl2dqY/3fK0viUN8Dh0P5yKV2zP7Ta gDNpcGm/dW7TTjnCUNcPvJSu48ojOqGGl604zVgS03tUJWmYUyZQxIj61ZS0myCIfpc6gw6kdt5 JOzrmqoVqv/fcVH22K5Hav8NcnF4ccE+xPpOPTyIe2vERZ+g4yyhSmhYMq3uQbqp6QQceuA5Zxz BzC82KKiKLdOItTIv8u60gMvRq6Xsc+J8NYqLu2l9J1Gv1s9j/bwLut7NuGqoQgzaHYpjS6M9la y1ZY6LMnsQzJ0K5Aq7b5wt9c7h1TgWdD3GDudh3j2GF78eUMorCjUAAG5f9GycexGTJmFzbI X-Proofpoint-GUID: LoPH5EDcyimy6RiDx2__teYG42tVWg9_ X-Proofpoint-ORIG-GUID: bL2U_lfo47QosROutIpsqzPzd2vFWyrx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_06,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=773 impostorscore=0 phishscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150155 Received-SPF: pass client-ip=148.163.158.5; envelope-from=milesg@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: milesg@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Glenn Miles On Mon, 2025-05-12 at 13:10 +1000, Nicholas Piggin wrote: > From: Michael Kowal > > Writes to the Flush Control registers were logged as invalid > when they are allowed. Clearing the unsupported want_cache_disable > feature is supported, so don't log an error in that case. > > Signed-off-by: Michael Kowal > --- > hw/intc/pnv_xive2.c | 36 ++++++++++++++++++++++++++++++++---- > 1 file changed, 32 insertions(+), 4 deletions(-) > > diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c > index 3c26cd6b77..c9374f0eee 100644 > --- a/hw/intc/pnv_xive2.c > +++ b/hw/intc/pnv_xive2.c > @@ -1411,7 +1411,14 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset, > /* > * ESB cache updates (not modeled) > */ > - /* case VC_ESBC_FLUSH_CTRL: */ > + case VC_ESBC_FLUSH_CTRL: > + if (val & VC_ESBC_FLUSH_CTRL_WANT_CACHE_DISABLE) { > + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx > + " value 0x%"PRIx64" bit[2] poll_want_cache_disable", > + offset, val); > + return; > + } > + break; > case VC_ESBC_FLUSH_POLL: > xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |= VC_ESBC_FLUSH_CTRL_POLL_VALID; > /* ESB update */ > @@ -1427,7 +1434,14 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset, > /* > * EAS cache updates (not modeled) > */ > - /* case VC_EASC_FLUSH_CTRL: */ > + case VC_EASC_FLUSH_CTRL: > + if (val & VC_EASC_FLUSH_CTRL_WANT_CACHE_DISABLE) { > + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx > + " value 0x%"PRIx64" bit[2] poll_want_cache_disable", > + offset, val); > + return; > + } > + break; > case VC_EASC_FLUSH_POLL: > xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |= VC_EASC_FLUSH_CTRL_POLL_VALID; > /* EAS update */ > @@ -1466,7 +1480,14 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset, > break; > > > - /* case VC_ENDC_FLUSH_CTRL: */ > + case VC_ENDC_FLUSH_CTRL: > + if (val & VC_ENDC_FLUSH_CTRL_WANT_CACHE_DISABLE) { > + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx > + " value 0x%"PRIx64" bit[2] poll_want_cache_disable", > + offset, val); > + return; > + } > + break; > case VC_ENDC_FLUSH_POLL: > xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |= VC_ENDC_FLUSH_CTRL_POLL_VALID; > break; > @@ -1687,7 +1708,14 @@ static void pnv_xive2_ic_pc_write(void *opaque, hwaddr offset, > pnv_xive2_nxc_update(xive, watch_engine); > break; > > - /* case PC_NXC_FLUSH_CTRL: */ > + case PC_NXC_FLUSH_CTRL: > + if (val & PC_NXC_FLUSH_CTRL_WANT_CACHE_DISABLE) { > + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx > + " value 0x%"PRIx64" bit[2] poll_want_cache_disable", > + offset, val); > + return; > + } > + break; > case PC_NXC_FLUSH_POLL: > xive->pc_regs[PC_NXC_FLUSH_CTRL >> 3] |= PC_NXC_FLUSH_CTRL_POLL_VALID; > break;