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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-71d7255f7bfsm288268a34.38.2024.11.28.05.07.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Nov 2024 05:07:59 -0800 (PST) Message-ID: <9ab8dd47-d9ff-4a1c-83de-71f4c04c8967@linaro.org> Date: Thu, 28 Nov 2024 07:07:57 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH for-10.0 01/25] fpu: handle raising Invalid for infzero in pick_nan_muladd To: Peter Maydell , qemu-devel@nongnu.org References: <20241128104310.3452934-1-peter.maydell@linaro.org> <20241128104310.3452934-2-peter.maydell@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20241128104310.3452934-2-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c35; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/28/24 04:42, Peter Maydell wrote: > For IEEE fused multiply-add, the (0 * inf) + NaN case should raise > Invalid for the multiplication of 0 by infinity. Currently we handle > this in the per-architecture ifdef ladder in pickNaNMulAdd(). > However, since this isn't really architecture specific we can hoist > it up to the generic code. > > For the cases where the infzero test in pickNaNMulAdd was > returning 2, we can delete the check entirely and allow the > code to fall into the normal pick-a-NaN handling, because this > will return 2 anyway (input 'c' being the only NaN in this case). > For the cases where infzero was returning 3 to indicate "return > the default NaN", we must retain that "return 3". > > For Arm, this looks like it might be a behaviour change because we > used to set float_flag_invalid | float_flag_invalid_imz only if C is > a quiet NaN. However, it is not, because Arm target code never looks > at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we > already raised float_flag_invalid via the "abc_mask & > float_cmask_snan" check in pick_nan_muladd. > > For any target architecture using the "default implementation" at the > bottom of the ifdef, this is a behaviour change but will be fixing a > bug (where we failed to raise the Invalid exception for (0 * inf + > QNaN). The architectures using the default case are: > * hppa > * sh4 > * tricore > > The Tricore and SH4 CPU architecture manuals are clear that this > should have raised Invalid; HPPA is a bit vaguer but still seems > clear enough. > > Signed-off-by: Peter Maydell > --- > fpu/softfloat-parts.c.inc | 13 +++++++------ > fpu/softfloat-specialize.c.inc | 29 +---------------------------- > 2 files changed, 8 insertions(+), 34 deletions(-) Reviewed-by: Richard Henderson r~