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[176.184.5.52]) by smtp.gmail.com with ESMTPSA id c2-20020a0564021f8200b0056bfca6f1c0sm811958edc.15.2024.03.28.06.18.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Mar 2024 06:18:44 -0700 (PDT) Message-ID: <9ac30d29-6ad6-44fb-96ad-22ed16489c73@linaro.org> Date: Thu, 28 Mar 2024 14:18:42 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] target/ppc: Fix broadcast tlbie synchronisation To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: Richard Henderson , Paolo Bonzini , qemu-devel@nongnu.org References: <20240328053131.2604454-1-npiggin@gmail.com> <20240328053131.2604454-2-npiggin@gmail.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240328053131.2604454-2-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=philmd@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 28/3/24 06:31, Nicholas Piggin wrote: > With mttcg, broadcast tlbie instructions do not wait until other vCPUs > have been kicked out of TCG execution before they complete (including > necessary subsequent tlbsync, etc., instructions). This is contrary to > the ISA, and it permits other vCPUs to use translations after the TLB > flush. For example: > > CPU0 > // *memP is initially 0, memV maps to memP with *pte > *pte = 0; > ptesync ; tlbie ; eieio ; tlbsync ; ptesync > *memP = 1; > > CPU1 > assert(*memV == 0); > > It is possible for the assertion to fail because CPU1 translates memV > using the TLB after CPU0 has stored 1 to the underlying memory. This > race was observed with a careful test case where CPU1 checks run in a > very large expensive TB so it can run for the entire CPU0 period between > clearing the pte and storing the memory. It's normally very difficult to > hit, but preemption of host vCPU threads could trigger the race > anywhere. > > Signed-off-by: Nicholas Piggin > --- > target/ppc/helper_regs.c | 2 +- > target/ppc/mmu_helper.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) To the best of my knowledge, Reviewed-by: Philippe Mathieu-Daudé