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Thu, 13 Mar 2025 18:45:32 +0000 (GMT) Message-ID: <9ac7ec4f-912c-4970-97d5-4a51d499a148@linux.ibm.com> Date: Fri, 14 Mar 2025 00:15:31 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/7] hw/ppc: Implement S0 SBE interrupt as cpu_pause then host reset To: Harsh Prateek Bora , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Nicholas Piggin , =?UTF-8?B?RnLDqWTDqXJpYyBCYXJyYXQ=?= , Sourabh Jain , Mahesh J Salgaonkar , Hari Bathini References: <20250217071934.86131-1-adityag@linux.ibm.com> <20250217071934.86131-3-adityag@linux.ibm.com> <2ef62054-7362-42a6-82c9-6fe7c3225a52@linux.ibm.com> Content-Language: en-US From: Aditya Gupta In-Reply-To: <2ef62054-7362-42a6-82c9-6fe7c3225a52@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: fJxK7UFbfyrJ9IpCYoBSP0uz9CaMwiZe X-Proofpoint-ORIG-GUID: kIGrJyhBL3M4HI2kRxT7UIFSFQs5g36A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_08,2025-03-13_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 spamscore=0 impostorscore=0 bulkscore=0 clxscore=1015 mlxscore=0 phishscore=0 adultscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503130141 Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/03/25 10:15, Harsh Prateek Bora wrote: > > > On 2/17/25 12:49, Aditya Gupta wrote: >> <...snip...> >> >> diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c >> index 62c94a04a2df..a6bf13650f2d 100644 >> --- a/hw/ppc/pnv_sbe.c >> +++ b/hw/ppc/pnv_sbe.c >> @@ -21,6 +21,8 @@ >>   #include "qapi/error.h" >>   #include "qemu/log.h" >>   #include "qemu/module.h" >> +#include "system/cpus.h" >> +#include "system/runstate.h" >>   #include "hw/irq.h" >>   #include "hw/qdev-properties.h" >>   #include "hw/ppc/pnv.h" >> @@ -80,6 +82,15 @@ >>   #define SBE_CONTROL_REG_S0              PPC_BIT(14) >>   #define SBE_CONTROL_REG_S1              PPC_BIT(15) >>   +static void pnv_sbe_set_host_doorbell(PnvSBE *sbe, uint64_t val) >> +{ >> +    val &= SBE_HOST_RESPONSE_MASK; /* Is this right? What does HW >> do? */ >> +    sbe->host_doorbell = val; >> + >> +    trace_pnv_sbe_reg_set_host_doorbell(val); >> +    qemu_set_irq(sbe->psi_irq, !!val); >> +} >> + >>   struct sbe_msg { >>       uint64_t reg[4]; >>   }; >> @@ -104,6 +115,7 @@ static uint64_t >> pnv_sbe_power9_xscom_ctrl_read(void *opaque, hwaddr addr, >>   static void pnv_sbe_power9_xscom_ctrl_write(void *opaque, hwaddr addr, >>                                          uint64_t val, unsigned size) >>   { >> +    PnvSBE *sbe = opaque; >>       uint32_t offset = addr >> 3; >>         trace_pnv_sbe_xscom_ctrl_write(addr, val); >> @@ -113,6 +125,35 @@ static void pnv_sbe_power9_xscom_ctrl_write(void >> *opaque, hwaddr addr, >>           switch (val) { >>           case SBE_CONTROL_REG_S0: >>               qemu_log_mask(LOG_UNIMP, "SBE: S0 Interrupt triggered\n"); >> + >> +            pnv_sbe_set_host_doorbell(sbe, sbe->host_doorbell | >> SBE_HOST_RESPONSE_MASK); >> + >> +            /* >> +             * Looks like, SBE stops clocks for all cores in S0. >> +             * See 'stopClocksS0' in SBE source code. >> +             * Nearest equivalent in QEMU seems to be 'pause_all_vcpus' >> +             */ >> +            pause_all_vcpus(); >> + >> +            /* >> +             * TODO: Pass `mpipl` node in device tree to signify next >> +             * boot is an MPIPL boot >> +             */ >> + >> +            /* Then do a guest reset */ >> +            /* >> +             * Requirement: >> +             * This guest reset should not clear the memory (which is >> +             * the case when this is merged) > > This comment may need a rephrase. Also, if we are keeping an > assumption that SHUTDOWN_CAUSE_GUEST_RESET should not clear the > memory, it may be better to put a comment about this wherever it is > handled as well. Sure, will make the comment more direct. > >> +             */ >> + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); >> + >> +            /* >> +             * XXX: Does SBE really do system reset or only stop >> +             * clocks ? OPAL seems to think that control will not come >> +             * to it after it has triggered S0 interrupt. >> +             */ >> + >>               break; >>           case SBE_CONTROL_REG_S1: >>               qemu_log_mask(LOG_UNIMP, "SBE: S1 Interrupt triggered\n"); >> @@ -138,15 +179,6 @@ static const MemoryRegionOps >> pnv_sbe_power9_xscom_ctrl_ops = { >>       .endianness = DEVICE_BIG_ENDIAN, >>   }; >>   -static void pnv_sbe_set_host_doorbell(PnvSBE *sbe, uint64_t val) >> -{ >> -    val &= SBE_HOST_RESPONSE_MASK; /* Is this right? What does HW >> do? */ >> -    sbe->host_doorbell = val; >> - >> -    trace_pnv_sbe_reg_set_host_doorbell(val); >> -    qemu_set_irq(sbe->psi_irq, !!val); >> -} >> - > > Code movement like above could be a separate patch, not necessary though. > Patch 1 can be squashed with this one. Got it, will move it to a separate patch, and squash patch 1 and the other parts of this patch. Thanks, - Aditya G > > Thanks > Harsh >>   /* SBE Target Type */ >>   #define SBE_TARGET_TYPE_PROC            0x00 >>   #define SBE_TARGET_TYPE_EX              0x01