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Wed, 14 May 2025 18:50:52 +0000 (GMT) Message-ID: <9b1537e1-9c40-47c1-ab92-8adda3d0b554@linux.ibm.com> Date: Wed, 14 May 2025 13:50:51 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 07/50] ppc/xive2: Reset Generation Flipped bit on END Cache Watch To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, =?UTF-8?B?RnLDqWTDqXJpYyBCYXJyYXQ=?= , Glenn Miles , Caleb Schlossin References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-8-npiggin@gmail.com> Content-Language: en-US From: Mike Kowal In-Reply-To: <20250512031100.439842-8-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=ZYgdNtVA c=1 sm=1 tr=0 ts=6824e60f cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VnNF1IyMAAAA:8 a=u5XRYQ9GfIdERzJa8uoA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: S4hSHrqmBY_vzIcdAkiKK-0jFjvCuEnh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE0MDE2OSBTYWx0ZWRfX8DBXd2FDq4+4 uOwVYdXyktTR0CZSRwe4SeKO8oWHIArB2JxtKu6la0Mqcnh/OHWSZ/M194yJJ+Oy4+T98U64FzZ r8d4DRrUgSKh+mymfV//1ghJXEGZTosaGiMJfH+FMhYsHA+GqVxi/ujtb1Yz/hwgdV6C9i1UxXN Uz+Z2UgmHeVOClzIcP7X4uPRTSed+Rp8IOwuXmkfzBJMJghgZIz1p21HsZabhOvKXGMt7+37EES cwB9aHoQcnMr9DsBN8UVn6O8lvmEHCXd6qeuopkSmncX/GVQn7cbfKTxs96bi2UYmWWwpo4uFhL 0Z4N7Xt1+QekS09sRJVjFUmvJ4TRinJG7ERMkuU7nigPbV6E2VB8xb6lwP6a/8B42KeLCrO3fS5 YLHe/oyuvHm3THr8/vyiHHGNIIZl6ndN2JiktvSlmArNfSMZmhv+rG/BIE6KV2FfZZ77VPXP X-Proofpoint-GUID: lYjjQVEOdLL5MqHyY5urrbyIwjkuSsGy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_04,2025-05-14_03,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 suspectscore=0 bulkscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505140169 Received-SPF: pass client-ip=148.163.158.5; envelope-from=kowal@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/11/2025 10:10 PM, Nicholas Piggin wrote: > From: Michael Kowal > > When the END Event Queue wraps the END EQ Generation bit is flipped and the > Generation Flipped bit is set to one. On a END cache Watch read operation, > the Generation Flipped bit needs to be reset. > > While debugging an error modified END not valid error messages to include > the method since all were the same. Reviewed-by: Michael Kowal Thanks MAK > > Signed-off-by: Michael Kowal > --- > hw/intc/pnv_xive2.c | 3 ++- > hw/intc/xive2.c | 4 ++-- > 2 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c > index 30b4ab2efe..72cdf0f20c 100644 > --- a/hw/intc/pnv_xive2.c > +++ b/hw/intc/pnv_xive2.c > @@ -1325,10 +1325,11 @@ static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwaddr offset, > case VC_ENDC_WATCH3_DATA0: > /* > * Load DATA registers from cache with data requested by the > - * SPEC register > + * SPEC register. Clear gen_flipped bit in word 1. > */ > watch_engine = (offset - VC_ENDC_WATCH0_DATA0) >> 6; > pnv_xive2_end_cache_load(xive, watch_engine); > + xive->vc_regs[reg] &= ~(uint64_t)END2_W1_GEN_FLIPPED; > val = xive->vc_regs[reg]; > break; > > diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c > index 4dd04a0398..453fe37f18 100644 > --- a/hw/intc/xive2.c > +++ b/hw/intc/xive2.c > @@ -374,8 +374,8 @@ static void xive2_end_enqueue(Xive2End *end, uint32_t data) > qgen ^= 1; > end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); > > - /* TODO(PowerNV): reset GF bit on a cache watch operation */ > - end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen); > + /* Set gen flipped to 1, it gets reset on a cache watch operation */ > + end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, 1); > } > end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); > }