From: Yi Liu <yi.l.liu@intel.com>
To: Zhenzhong Duan <zhenzhong.duan@intel.com>, <qemu-devel@nongnu.org>
Cc: <alex.williamson@redhat.com>, <clg@redhat.com>,
<eric.auger@redhat.com>, <mst@redhat.com>, <peterx@redhat.com>,
<jasowang@redhat.com>, <jgg@nvidia.com>, <nicolinc@nvidia.com>,
<joao.m.martins@oracle.com>, <clement.mathieu--drif@eviden.com>,
<kevin.tian@intel.com>, <chao.p.peng@intel.com>,
Paolo Bonzini <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Subject: Re: [PATCH v2 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting
Date: Wed, 14 Aug 2024 20:22:59 +0800 [thread overview]
Message-ID: <9b2b2f76-a5ef-4378-b233-af1a44f742c7@intel.com> (raw)
In-Reply-To: <20240805062727.2307552-17-zhenzhong.duan@intel.com>
On 2024/8/5 14:27, Zhenzhong Duan wrote:
> When host IOMMU doesn't support FS1GP but vIOMMU does, host IOMMU
> can't translate stage-1 page table from guest correctly.
this series is for emulated devices, so the above statement does not
belong to this series. Is there any other reason to have this option?
> Add a property x-cap-fs1gp for user to turn FS1GP off so that
> nested page table on host side works.
I guess you would need to sync the FS1GP cap with host before reporting it
in vIOMMU when comes to support passthrough devices.
> This property has no effect when vIOMMU isn't in scalable modern
> mode.
>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> ---
> include/hw/i386/intel_iommu.h | 1 +
> hw/i386/intel_iommu.c | 5 ++++-
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
> index 650641544c..f6d9b41b80 100644
> --- a/include/hw/i386/intel_iommu.h
> +++ b/include/hw/i386/intel_iommu.h
> @@ -308,6 +308,7 @@ struct IntelIOMMUState {
> bool dma_drain; /* Whether DMA r/w draining enabled */
> bool dma_translation; /* Whether DMA translation supported */
> bool pasid; /* Whether to support PASID */
> + bool fs1gp; /* First Stage 1-GByte Page Support */
>
> /*
> * Protects IOMMU states in general. Currently it protects the
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 9e973bd710..d7e7354db4 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -3778,6 +3778,7 @@ static Property vtd_properties[] = {
> DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false),
> DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),
> DEFINE_PROP_BOOL("dma-translation", IntelIOMMUState, dma_translation, true),
> + DEFINE_PROP_BOOL("x-cap-fs1gp", IntelIOMMUState, fs1gp, true),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> @@ -4506,7 +4507,9 @@ static void vtd_cap_init(IntelIOMMUState *s)
> /* TODO: read cap/ecap from host to decide which cap to be exposed. */
> if (s->scalable_modern) {
> s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_FLTS;
> - s->cap |= VTD_CAP_FS1GP;
> + if (s->fs1gp) {
> + s->cap |= VTD_CAP_FS1GP;
> + }
> } else if (s->scalable_mode) {
> s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS;
> }
--
Regards,
Yi Liu
next prev parent reply other threads:[~2024-08-14 12:19 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-05 6:27 [PATCH v2 00/17] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-08-05 6:27 ` [PATCH v2 01/17] intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan
2024-08-13 10:57 ` Yi Liu
2024-08-14 2:30 ` Duan, Zhenzhong
2024-08-05 6:27 ` [PATCH v2 02/17] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-08-13 12:10 ` Yi Liu
2024-08-05 6:27 ` [PATCH v2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode Zhenzhong Duan
2024-08-06 6:35 ` CLEMENT MATHIEU--DRIF
2024-08-08 12:31 ` Duan, Zhenzhong
2024-08-08 15:04 ` CLEMENT MATHIEU--DRIF
2024-08-13 2:20 ` Duan, Zhenzhong
2024-08-13 5:22 ` CLEMENT MATHIEU--DRIF
2024-08-13 6:26 ` Duan, Zhenzhong
2024-08-13 6:58 ` CLEMENT MATHIEU--DRIF
2024-08-05 6:27 ` [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-08-06 6:35 ` CLEMENT MATHIEU--DRIF
2024-08-08 12:40 ` Duan, Zhenzhong
2024-08-08 14:56 ` CLEMENT MATHIEU--DRIF
2024-08-13 2:12 ` Duan, Zhenzhong
2024-08-13 7:13 ` CLEMENT MATHIEU--DRIF
2024-08-13 7:18 ` CLEMENT MATHIEU--DRIF
2024-08-14 12:36 ` Yi Liu
2024-08-15 5:48 ` Duan, Zhenzhong
2024-08-19 9:03 ` Yi Liu
2024-08-05 6:27 ` [PATCH v2 05/17] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-08-05 6:27 ` [PATCH v2 06/17] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-08-05 6:27 ` [PATCH v2 07/17] intel_iommu: Check if the input address is canonical Zhenzhong Duan
2024-08-14 12:02 ` Yi Liu
2024-08-16 2:19 ` Duan, Zhenzhong
2024-08-05 6:27 ` [PATCH v2 08/17] intel_iommu: Set accessed and dirty bits during first stage translation Zhenzhong Duan
2024-08-14 11:45 ` Yi Liu
2024-08-16 2:37 ` Duan, Zhenzhong
2024-08-16 4:29 ` CLEMENT MATHIEU--DRIF
2024-08-16 4:22 ` CLEMENT MATHIEU--DRIF
2024-08-05 6:27 ` [PATCH v2 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-08-05 6:27 ` [PATCH v2 10/17] intel_iommu: Process PASID-based " Zhenzhong Duan
2024-08-05 6:27 ` [PATCH v2 11/17] intel_iommu: Add an internal API to find an address space with PASID Zhenzhong Duan
2024-08-05 6:27 ` [PATCH v2 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation Zhenzhong Duan
2024-08-05 6:27 ` [PATCH v2 13/17] intel_iommu: piotlb invalidation should notify unmap Zhenzhong Duan
2024-08-19 9:35 ` Yi Liu
2024-08-19 9:57 ` Duan, Zhenzhong
2024-08-20 2:43 ` Yi Liu
2024-08-20 2:54 ` Duan, Zhenzhong
2024-08-05 6:27 ` [PATCH v2 14/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode Zhenzhong Duan
2024-08-06 6:35 ` CLEMENT MATHIEU--DRIF
2024-08-14 12:26 ` Yi Liu
2024-08-15 3:39 ` Duan, Zhenzhong
2024-08-05 6:27 ` [PATCH v2 15/17] intel_iommu: Modify x-scalable-mode to be string option to expose scalable modern mode Zhenzhong Duan
2024-08-06 6:34 ` CLEMENT MATHIEU--DRIF
2024-08-08 12:28 ` Duan, Zhenzhong
2024-08-05 6:27 ` [PATCH v2 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting Zhenzhong Duan
2024-08-06 6:33 ` CLEMENT MATHIEU--DRIF
2024-08-14 12:22 ` Yi Liu [this message]
2024-08-15 3:46 ` Duan, Zhenzhong
2024-08-19 9:30 ` Yi Liu
2024-08-19 9:41 ` Duan, Zhenzhong
2024-08-19 12:16 ` Yi Liu
2024-08-05 6:27 ` [PATCH v2 17/17] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-08-12 7:29 ` Thomas Huth
2024-09-10 11:29 ` [PATCH v2 00/17] intel_iommu: Enable stage-1 translation for emulated device CLEMENT MATHIEU--DRIF
2024-09-11 2:29 ` Duan, Zhenzhong
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=9b2b2f76-a5ef-4378-b233-af1a44f742c7@intel.com \
--to=yi.l.liu@intel.com \
--cc=alex.williamson@redhat.com \
--cc=chao.p.peng@intel.com \
--cc=clement.mathieu--drif@eviden.com \
--cc=clg@redhat.com \
--cc=eduardo@habkost.net \
--cc=eric.auger@redhat.com \
--cc=jasowang@redhat.com \
--cc=jgg@nvidia.com \
--cc=joao.m.martins@oracle.com \
--cc=kevin.tian@intel.com \
--cc=marcel.apfelbaum@gmail.com \
--cc=mst@redhat.com \
--cc=nicolinc@nvidia.com \
--cc=pbonzini@redhat.com \
--cc=peterx@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=zhenzhong.duan@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).