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Wed, 30 Jul 2025 13:53:45 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31f63da57b4sm2848303a91.5.2025.07.30.13.53.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Jul 2025 13:53:44 -0700 (PDT) Message-ID: <9b3b9cdd-c6d5-4c98-8fd9-be0402ad1804@linaro.org> Date: Wed, 30 Jul 2025 13:53:44 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 24/82] include/hw/core/cpu: Introduce cpu_tlb_fast Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org References: <20250727080254.83840-1-richard.henderson@linaro.org> <20250727080254.83840-25-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20250727080254.83840-25-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/27/25 1:01 AM, Richard Henderson wrote: > Encapsulate access to cpu->neg.tlb.f[] in a function. > > Signed-off-by: Richard Henderson > --- > include/hw/core/cpu.h | 7 +++++++ > accel/tcg/cputlb.c | 16 ++++++++-------- > 2 files changed, 15 insertions(+), 8 deletions(-) > > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h > index 1153cadb70..bd835b07d5 100644 > --- a/include/hw/core/cpu.h > +++ b/include/hw/core/cpu.h > @@ -593,6 +593,13 @@ static inline CPUArchState *cpu_env(CPUState *cpu) > return (CPUArchState *)(cpu + 1); > } > > +#ifdef CONFIG_TCG > +static inline CPUTLBDescFast *cpu_tlb_fast(CPUState *cpu, int mmu_idx) > +{ > + return &cpu->neg.tlb.f[mmu_idx]; > +} > +#endif > + > typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; > extern CPUTailQ cpus_queue; > > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index d324f33339..2a6aa01c57 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -129,7 +129,7 @@ static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry) > static inline uintptr_t tlb_index(CPUState *cpu, uintptr_t mmu_idx, > vaddr addr) > { > - uintptr_t size_mask = cpu->neg.tlb.f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS; > + uintptr_t size_mask = cpu_tlb_fast(cpu, mmu_idx)->mask >> CPU_TLB_ENTRY_BITS; > > return (addr >> TARGET_PAGE_BITS) & size_mask; > } > @@ -138,7 +138,7 @@ static inline uintptr_t tlb_index(CPUState *cpu, uintptr_t mmu_idx, > static inline CPUTLBEntry *tlb_entry(CPUState *cpu, uintptr_t mmu_idx, > vaddr addr) > { > - return &cpu->neg.tlb.f[mmu_idx].table[tlb_index(cpu, mmu_idx, addr)]; > + return &cpu_tlb_fast(cpu, mmu_idx)->table[tlb_index(cpu, mmu_idx, addr)]; > } > > static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, > @@ -292,7 +292,7 @@ static void tlb_flush_one_mmuidx_locked(CPUState *cpu, int mmu_idx, > int64_t now) > { > CPUTLBDesc *desc = &cpu->neg.tlb.d[mmu_idx]; > - CPUTLBDescFast *fast = &cpu->neg.tlb.f[mmu_idx]; > + CPUTLBDescFast *fast = cpu_tlb_fast(cpu, mmu_idx); > > tlb_mmu_resize_locked(desc, fast, now); > tlb_mmu_flush_locked(desc, fast); > @@ -331,7 +331,7 @@ void tlb_init(CPUState *cpu) > cpu->neg.tlb.c.dirty = 0; > > for (i = 0; i < NB_MMU_MODES; i++) { > - tlb_mmu_init(&cpu->neg.tlb.d[i], &cpu->neg.tlb.f[i], now); > + tlb_mmu_init(&cpu->neg.tlb.d[i], cpu_tlb_fast(cpu, i), now); > } > } > > @@ -342,7 +342,7 @@ void tlb_destroy(CPUState *cpu) > qemu_spin_destroy(&cpu->neg.tlb.c.lock); > for (i = 0; i < NB_MMU_MODES; i++) { > CPUTLBDesc *desc = &cpu->neg.tlb.d[i]; > - CPUTLBDescFast *fast = &cpu->neg.tlb.f[i]; > + CPUTLBDescFast *fast = cpu_tlb_fast(cpu, i); > > g_free(fast->table); > g_free(desc->fulltlb); > @@ -667,7 +667,7 @@ static void tlb_flush_range_locked(CPUState *cpu, int midx, > unsigned bits) > { > CPUTLBDesc *d = &cpu->neg.tlb.d[midx]; > - CPUTLBDescFast *f = &cpu->neg.tlb.f[midx]; > + CPUTLBDescFast *f = cpu_tlb_fast(cpu, midx); > vaddr mask = MAKE_64BIT_MASK(0, bits); > > /* > @@ -923,7 +923,7 @@ void tlb_reset_dirty(CPUState *cpu, uintptr_t start, uintptr_t length) > qemu_spin_lock(&cpu->neg.tlb.c.lock); > for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { > CPUTLBDesc *desc = &cpu->neg.tlb.d[mmu_idx]; > - CPUTLBDescFast *fast = &cpu->neg.tlb.f[mmu_idx]; > + CPUTLBDescFast *fast = cpu_tlb_fast(cpu, mmu_idx); > unsigned int n = tlb_n_entries(fast); > unsigned int i; > > @@ -1316,7 +1316,7 @@ static bool victim_tlb_hit(CPUState *cpu, size_t mmu_idx, size_t index, > > if (cmp == page) { > /* Found entry in victim tlb, swap tlb and iotlb. */ > - CPUTLBEntry tmptlb, *tlb = &cpu->neg.tlb.f[mmu_idx].table[index]; > + CPUTLBEntry tmptlb, *tlb = &cpu_tlb_fast(cpu, mmu_idx)->table[index]; > > qemu_spin_lock(&cpu->neg.tlb.c.lock); > copy_tlb_helper_locked(&tmptlb, tlb); It's sad, my eyes were just getting used to read those accesses :) More seriously, that's clearer, thanks. Reviewed-by: Pierrick Bouvier