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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id y2sm2645633pfq.16.2020.05.01.09.13.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 01 May 2020 09:13:48 -0700 (PDT) Subject: Re: [PATCH 23/36] target/arm: Convert Neon 64-bit element 3-reg-same insns To: Peter Maydell References: <20200430181003.21682-1-peter.maydell@linaro.org> <20200430181003.21682-24-peter.maydell@linaro.org> <366a2e79-d963-bfdc-fcc6-2a63026fa1db@linaro.org> From: Richard Henderson Message-ID: <9b4cfbec-2fd3-3674-4622-1f0caccb43ed@linaro.org> Date: Fri, 1 May 2020 09:13:46 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/1/20 8:54 AM, Peter Maydell wrote: > On Thu, 30 Apr 2020 at 21:54, Richard Henderson > wrote: >> >> On 4/30/20 11:09 AM, Peter Maydell wrote: >>> + >>> + rn = tcg_temp_new_i64(); >>> + rm = tcg_temp_new_i64(); >>> + rd = tcg_temp_new_i64(); >>> + >>> + for (pass = 0; pass < (a->q ? 2 : 1); pass++) { >>> + neon_load_reg64(rn, a->vn + pass); >>> + neon_load_reg64(rm, a->vm + pass); >>> + fn(rd, rm, rn); >>> + neon_store_reg64(rd, a->vd + pass); >>> + } >>> + >>> + tcg_temp_free_i64(rn); >>> + tcg_temp_free_i64(rm); >>> + tcg_temp_free_i64(rd); >>> + >>> + return true; >>> +} >>> + >>> +#define DO_3SAME_64(INSN, FUNC) \ >>> + static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ >>> + { \ >>> + return do_3same_64(s, a, FUNC); \ >>> + } >> >> You can morph this into the gvec interface like so: >> >> #define DO_3SAME_64(INSN, FUNC) \ >> static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, >> uint32_t rn_ofs, uint32_t rm_ofs, >> uint32_t oprsz, uint32_t maxsz) >> { >> static const GVecGen3 op = { .fni8 = FUNC }; >> tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, >> oprsz, maxsz, &op); >> } >> DO_3SAME(INSN, gen_##INSN##_3s) >> >> The .fni8 function tells gvec that we have a helper that processes the >> operation in 8 byte chunks. It will handle the pass loop for you. > > This doesn't quite work, because these are shift ops and > so the operands are passed to the helper in the order > rd, rm, rn. Reshuffling the order of arguments to > tcg_gen_gvec_3() fixes this, though. > > I guess I should call the macro DO_3SAME_SHIFT64, I hadn't > noticed it was shift specific because the only thing we do > with it is shifts. See my reply to patch 26. I think we should swap these operands during decode. r~