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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id f17sm12223582wmc.8.2019.12.13.17.39.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Dec 2019 17:39:00 -0800 (PST) Subject: Re: MIPS cache bypass on custom board To: "Bensch, Alexander" , "qemu-devel@nongnu.org" References: From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <9ba23651-746a-5085-eff8-a048385e29ed@redhat.com> Date: Sat, 14 Dec 2019 02:38:59 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: AOlZ2BwyPziPAkT9QZdy2g-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Alexander, On 12/13/19 7:59 PM, Bensch, Alexander wrote: > Hi all, >=20 > Currently stuck on a problem in QEMU 4.0.0. I=92m trying to implement a= =20 > custom device using a MIPS 24Kc CPU. The device boots from an SPI flash= =20 > device that is mapped to 0x9F000000 (physical address 0x1F000000). I got= =20 > the initial load and execute working by direct loading a flash dump to a= =20 > MemoryRegion based at 0x1F000000, which worked great until the ROM=20 > needed to access the SPI registers that are addressed to 0xBF000000=20 > (/also /physical address 0x1F000000). QEMU cannot differentiate reads=20 > and writes to 0xBF000000 from reads and writes to 0x9F000000. >=20 > Initially I assumed this was a caching problem, as I know that the SPI=20 > registers are located in the KSEG1 memory segment which uses uncached=20 > writes, while the flash mapping is in KSEG0 with cached writes. I also=20 > can see that QEMU has logic to handle caching in a few source files=20 > within /targets/mips//. However, when I read from addresses in the KSEG1= =20 > region, I still see contents from the KSEG0 region. >=20 > My question is whether there is any way to configure a MIPS board such=20 > that I can correctly bypass the cache for KSEG1 as expressed by the MIPS= =20 > documentation? Unfortunately QEMU doesn't model microarchitecture, thus no cache is=20 modelled, meaning KSEG1 is the same as KSEG0. Peter Maydell had the similar problem you describe last year: https://www.mail-archive.com/qemu-devel@nongnu.org/msg556999.html >=20 > Apologies if details are lacking. Please request more info if needed. >=20 > Thank you, >=20 > *Alex Bensch*